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m68hc08 microcontrollers freescale.com mc68hc08gp32a mc68hc08gp16a data sheet mc68hc08gp32a rev. 1,0 03/2006

mc68hc08gp32a ? mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 3 freescale? and the freescale logo are trade marks of freescale semiconductor, inc. ? freescale semiconductor, inc., 2004, 2006. all rights reserved. mc68hc08gp32a mc68hc08gp16a data sheet to provide the most up-to-date information, the revisi on of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to verify you have the latest information available, refer to: http://freescale.com the following revision history table summarizes changes contained in this document. for your convenience, the page number designators have been linked to the appropriate location. revision history date revision level description page number(s) march, 2004 n/a initial release july, 2005 0.1 updated to meet freescale identity guidelines. throughout march, 2006 1.0 9.5 clock generator module (cgm) ? updated description to remove erroneous information. 94 20.16.1 cgm component specifications ? updated to reflect correct values. 249
revision history mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 4 freescale semiconductor
mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 5 list of chapters chapter 1 general descr iption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 chapter 2 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 chapter 3 analog-to-digital co nverter (adc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 chapter 4 clock generator module (cgm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 chapter 5 computer operating properly (cop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 chapter 6 central processor unit (cpu). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 chapter 7 external interrupt (i rq) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 chapter 8 keyboard interrupt (kbi) module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 chapter 9 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 chapter 10 low-voltage inhi bit (lvi). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 chapter 11 mask option registers (mor2 and mor1) . . . . . . . . . . . . . . . . . . . . . . . . . . .103 chapter 12 input/output (i/o) port s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 chapter 13 resets and interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 chapter 14 serial communications in terface (sci) module . . . . . . . . . . . . . . . . . . . . . . .135 chapter 15 system integration module (sim) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 chapter 16 serial peripheral interface (spi) module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 chapter 17 timebase module (tbm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 chapter 18 timer interface modules (tim 1 and tim2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 chapter 19 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 chapter 20 electrical spec ifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 chapter 21 ordering information and mechanical specifications . . . . . . . . . . . . . . . . . . 251
list of chapters mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 6 freescale semiconductor
mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 7 table of contents chapter 1 general description 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.3 standard features of the mc68hc08gp32a and mc 68hc08gp16a . . . . . . . . . . . . . . . . . . . 19 1.3.1 features of the cpu08 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.4 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.5 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.6 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.6.1 power supply pins (v dd and v ss ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.6.2 oscillator pins (osc1 and osc2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.6.3 external reset pin (rst ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.6.4 external interrupt pin (irq ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.6.5 cgm power supply pins (v dda and v ssa ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.6.6 external filter capacitor pin (cgmxfc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.6.7 adc power supply/reference pins (v ddad /v refh and v ssad /v refl ). . . . . . . . . . . . . . . . 25 1.6.8 port a input/output (i/o) pins (pta7/kbd7 ?pta0/kbd0 ) . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.6.9 port b i/o pins (ptb7/ad7?ptb0/ad0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.6.10 port c i/o pins (ptc6?ptc0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.6.11 port d i/o pins (ptd7/t2ch1?ptd0/ss ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.6.12 port e i/o pins (pte1/rxd?pte0/txd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 chapter 2 memory 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.2 unimplemented memory locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.3 reserved memory locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.4 input/output (i/o) section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.5 random-access memory (ram) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.6 read-only memory (rom) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 chapter 3 analog-to-digital converter (adc) 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.3.1 adc port i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.3.2 voltage conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.3.3 conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.3.4 conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.3.5 accuracy and precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
table of contents mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 8 freescale semiconductor 3.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.6 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.6.1 adc analog power pin (v ddad )/adc voltage reference high pin (v refh ) . . . . . . . . . . . 43 3.6.2 adc analog ground pin (v ssad )/adc voltage reference low pin (v refl ) . . . . . . . . . . . 43 3.6.3 adc voltage in (v adin ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.7 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.7.1 adc status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.7.2 adc data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.7.3 adc clock register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 chapter 4 clock generator module (cgm) 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.3.1 crystal oscillator circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.3.2 phase-locked loop circuit (pll) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.3.3 pll circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.3.4 acquisition and tracking modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1 4.3.5 manual and automatic pll bandwidth modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.3.6 programming the pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4.3.7 special programming exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.3.8 base clock selector circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.3.9 cgm external connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.4.1 crystal amplifier input pin (osc1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.4.2 crystal amplifier output pin (osc2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.4.3 external filter capacitor pin (cgmxfc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.4.4 pll analog power pin (v dda ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.4.5 pll analog ground pin (v ssa ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.4.6 oscillator enable signal (simoscen) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.4.7 oscillator stop mode enable bit (oscstopenb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.4.8 crystal output frequency signal (cgmxclk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.4.9 cgm base clock output (cgmout) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.4.10 cgm cpu interrupt (cgmint) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.5 cgm registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.5.1 pll control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.5.2 pll bandwidth control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 0 4.5.3 pll multiplier select register high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.5.4 pll multiplier select register low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 4.5.5 pll vco range select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.5.6 pll reference divider select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 9 4.7 special modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.7.3 cgm during break interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.8 acquisition/lock time specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.8.1 acquisition/lock time definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.8.2 parametric influences on reaction time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.8.3 choosing a filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 chapter 5 computer operatin g properly (cop) 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.3 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.3.1 cgmxclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.3.2 stop instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.3.3 copctl write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.3.4 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.3.5 internal reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.3.6 copd (cop disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.3.7 coprs (cop rate select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.4 cop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.6 monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.8 cop module during break mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 9 chapter 6 central processor unit (cpu) 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.3.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.3.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.3.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.3.4 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.3.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.4 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.6 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.7 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.8 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
table of contents mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 10 freescale semiconductor chapter 7 external interrupt (irq) 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 7.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 7.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 7.4 irq pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.5 irq module during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 7.6 irq status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 chapter 8 keyboard interrupt (kbi) module 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 8.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 8.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 8.4 keyboard initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 8.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 8.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 8.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 8.6 keyboard module during break interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 8.7 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 8.7.1 keyboard status and control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 8.7.2 keyboard interrupt enable register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 chapter 9 low-power modes 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 9.1.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 9.1.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 9.2 analog-to-digital converter (adc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 9.2.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 9.2.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 9.3 break module (brk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 9.3.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 9.3.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 9.4 central processor unit (cpu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 9.4.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 9.4.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 9.5 clock generator module (cgm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 9.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 9.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 9.6 computer operating properly module (cop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 9.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 9.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 11 9.7 external interrupt module (irq). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 9.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 9.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 9.8 keyboard interrupt module (kbi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 9.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 9.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 9.9 low-voltage inhibit module (lvi). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 9.9.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 9.9.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 9.10 serial communications interface module (sci) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 9.10.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 9.10.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 9.11 serial peripheral interface module (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 9.11.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 9.11.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 9.12 timer interface module (tim1 and tim2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 9.12.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 9.12.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 9.13 timebase module (tbm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 9.13.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 9.13.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 9.14 exiting wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 9.15 exiting stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 chapter 10 low-voltage inhibit (lvi) 10.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 10.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 10.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 10.3.1 polled lvi operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 10.3.2 forced reset operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 10.3.3 voltage hysteresis protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 10.3.4 lvi trip selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 10.4 lvi status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 10.5 lvi interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 10.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 10.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 10.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 chapter 11 mask option register s (mor2 and mor1) 11.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 11.2 mask option registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
table of contents mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 12 freescale semiconductor chapter 12 input/output (i/o) ports 12.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 12.2 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 12.2.1 port a data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 12.2.2 data direction register a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 12.2.3 port a input pullup enable register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 12.3 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 12.3.1 port b data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 12.3.2 data direction register b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 12.4 port c. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 12.4.1 port c data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 12.4.2 data direction register c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 12.4.3 port c input pullup enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 12.5 port d. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 12.5.1 port d data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 12.5.2 data direction register d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 12.5.3 port d input pullup enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 12.6 port e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 12.6.1 port e data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 12.6.2 data direction register e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 chapter 13 resets and interrupts 13.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 13.2 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 13.2.1 effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 13.2.2 external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 13.2.3 internal reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 13.2.3.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 13.2.3.2 cop reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 13.2.3.3 low-voltage inhibit reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 13.2.3.4 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 13.2.3.5 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 13.2.4 sim reset status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 13.3 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 13.3.1 effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 13.3.2 sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 13.3.2.1 swi instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 13.3.2.2 break interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 13.3.2.3 irq pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 13.3.2.4 cgm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 13.3.2.5 tim1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 13.3.2.6 tim2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 13.3.2.7 spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 13.3.2.8 sci . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 13.3.2.9 kbd0 ?kbd7 pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 13 13.3.2.10 adc (analog-to-digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 13.3.2.11 tbm (timebase module) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 13.3.3 interrupt status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 13.3.3.1 interrupt status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 13.3.3.2 interrupt status register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 13.3.3.3 interrupt status register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 chapter 14 serial communications in terface (sci) module 14.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 14.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 14.3 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 14.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 14.4.1 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 14.4.2 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 14.4.2.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 14.4.2.2 character transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 14.4.2.3 break characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 14.4.2.4 idle characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 14.4.2.5 inversion of transmitted output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2 14.4.2.6 transmitter interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 14.4.3 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 14.4.3.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 14.4.3.2 character reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 14.4.3.3 data sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 14.4.3.4 framing errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 14.4.3.5 baud rate tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 14.4.3.6 receiver wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 14.4.3.7 receiver interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 14.4.3.8 error interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 14.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 14.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 14.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 14.6 sci during break module interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 14.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 14.7.1 pte0/txd (transmit data). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 14.7.2 pte1/rxd (receive data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 14.8 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 14.8.1 sci control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 14.8.2 sci control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 14.8.3 sci control register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 14.8.4 sci status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 14.8.5 sci status register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 14.8.6 sci data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 14.8.7 sci baud rate register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
table of contents mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 14 freescale semiconductor chapter 15 system integrati on module (sim) 15.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 15.2 sim bus clock control and generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 15.2.1 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 15.2.2 clock startup from por or lvi reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 15.2.3 clocks in stop mode and wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 15.3 reset and system initializat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 15.3.1 external pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 15.3.2 active resets from intern al sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 15.3.2.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 15.3.2.2 computer operating properly (cop) reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 15.3.2.3 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 15.3.2.4 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 15.3.2.5 low-voltage inhibit (lvi) reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 67 15.4 sim counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 15.4.1 sim counter during power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 15.4.2 sim counter during stop mode recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 15.4.3 sim counter and reset states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7 15.5 exception control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 15.5.1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 15.5.1.1 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 15.5.1.2 swi instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 15.5.1.3 interrupt status registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 15.5.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 15.5.3 break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 15.5.4 status flag protection in break mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 15.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 15.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 15.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 15.7 sim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 15.7.1 sim break status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 15.7.2 sim reset status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 15.7.3 sim break flag control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7 chapter 16 serial peripheral interface (spi) module 16.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 16.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 16.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 16.3.1 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 16.3.2 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 16.4 transmission formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 16.4.1 clock phase and polarity controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3 16.4.2 transmission format when cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 16.4.3 transmission format when cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 16.4.4 transmission initiation latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 15 16.5 queuing transmission data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 16.6 error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 16.6.1 overflow error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 16.6.2 mode fault error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 16.7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 16.8 resetting the spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 16.9 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 16.9.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 16.9.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 16.10 spi during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 16.11 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 16.11.1 miso (master in/slave out). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 16.11.2 mosi (master out/slave in). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 16.11.3 spsck (serial clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 16.11.4 ss (slave select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 16.12 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 16.12.1 spi control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 16.12.2 spi status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 16.12.3 spi data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 chapter 17 timebase module (tbm) 17.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 17.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 17.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 17.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 17.5 tbm interrupt rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 17.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 17.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 17.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 17.7 timebase control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 chapter 18 timer interface modules (tim1 and tim2) 18.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 18.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 18.3 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 18.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 18.4.1 tim counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 18.4.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 18.4.3 output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 18.4.3.1 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 18.4.3.2 buffered output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 08 18.4.4 pulse width modulation (pwm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 18.4.4.1 unbuffered pwm signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 18.4.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 18.4.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
table of contents mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 16 freescale semiconductor 18.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 18.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 18.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 18.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 18.7 tim during break interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 18.8 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 18.9 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 18.9.1 tim status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 12 18.9.2 tim counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 18.9.3 tim counter modulo registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4 18.9.4 tim channel status and control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 18.9.5 tim channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 chapter 19 development support 19.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 19.2 break module (brk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 19.2.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 19.2.1.1 flag protection during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 19.2.1.2 tim during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 19.2.1.3 cop during break in terrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 21 19.2.2 break module registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 19.2.2.1 break status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 19.2.2.2 break address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 19.2.2.3 break status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 19.2.2.4 break flag control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 19.2.3 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 19.3 monitor module (mon) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 19.3.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 19.3.1.1 monitor mode entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 19.3.1.2 monitor vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 19.3.1.3 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 19.3.1.4 break signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 19.3.1.5 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 19.3.2 security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 19.3.3 baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 chapter 20 electrical specifications 20.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 20.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 20.3 functional operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 20.4 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 20.5 5.0-v dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 20.6 3.0-v dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 20.7 5.0-v control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 17 20.8 3.0-v control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 20.9 output high-voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 20.10 output low-voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 20.11 typical supply currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 20.12 adc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 20.13 5.0-v spi characteri stics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 20.14 3.0-v spi characteri stics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 20.15 timer interface module characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 20.16 clock generation module characteristic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9 20.16.1 cgm component specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 20.16.2 cgm electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 20.17 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 chapter 21 ordering information and m echanical specifications 21.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 21.2 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
table of contents mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 18 freescale semiconductor
mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 19 chapter 1 general description 1.1 introduction the mc68hc08gp32a and mc68hc08gp16a are me mbers of the low-cost, high-performance m68hc08 family of 8-bit microcontroller units (m cus). all mcus in the family use the enhanced m68hc08 central processor unit (cpu08) and are avail able with a variety of modules, memory sizes and types, and package types. 1.2 features for convenience, features have been organized to reflect: standard features of the mc68hc08gp32a and mc68hc08gp16a features of the cpu08 1.3 standard features of th e mc68hc08gp32a and mc68hc08gp16a high-performance m68hc08 architecture optimized for c-compilers fully upward-compatible object code wi th m6805, m146805, and m68hc05 families 8-mhz internal bus frequency system protection features: ? optional computer operating properly (cop) reset ? low-voltage detection with optional reset and selectable trip points for 3.0-v and 5.0-v operation ? illegal opcode detection with reset ? illegal address detection with reset low-power design; fully static with stop and wait modes standard low-power modes of operation: ? wait mode ? stop mode master reset pin and power-on reset (por) on-chip read-only memory (rom) ? mc68hc08gp32a ? 32,256 bytes ? mc68hc08gp16a ? 15,872 bytes 512 bytes of on-chip random-access memory (ram) serial peripheral interface module (spi) serial communications interface module (sci) two 16-bit, 2-channel timer interface modules (tim1 and tim2) with selectable input capture, output compare, and pwm capability on each channel
general description mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 20 freescale semiconductor 8-channel, 8-bit successive approximati on analog-to-digital converter (adc) break module (brk) to allow single brea kpoint setting during in-circuit debugging internal pullups on irq and rst to reduce customer system cost clock generator module with on-chip 32-khz crystal compatible pll (phase-lock loop) up to 33 general-purpose input/output (i/o) pins, including: ? 26 shared-function i/o pins ? five or seven dedicated i/o pins, depending on package choice selectable pullups on inputs only on ports a, c, and d. selection is on an i ndividual port bit basis. during output mode, pullups are disengaged. high current 10-ma sink/10-ma sour ce capability on all port pins higher current 15-ma sink/source capability on ptc0?ptc4 timebase module with clock prescaler circuitry for eight user selectable periodic real-time interrupts with optional active clock source durin g stop mode for periodic wakeup from stop using an external 32-khz crystal 8-bit keyboard wakeup port 5-ma maximum current injection on all port pins to maintain input protection available packages: 42-pin shrink dual-in-line pa ckage (sdip) and 44-pin quad flat pack (qfp) specific features of the 42-pin sdip ? port c is only 5 bits: ptc0?ptc4 specific features of the 44-pin qfp ? port c is 7 bits: ptc0?ptc6 1.3.1 features of the cpu08 features of the cpu08 include: enhanced hc05 programming model extensive loop control functions 16 addressing modes (eight more than the hc05) 16-bit index register and stack pointer memory-to-memory data transfers fast 8 8 multiply instruction fast 16/8 divide instruction binary-coded decimal (bcd) instructions optimization for controller applications efficient c language support 1.4 mcu block diagram figure 1-1 shows the structure of the mc68hc08gp32a and mc68hc08gp16a.
mcu block diagram mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 21 figure 1-1. mcu block diagram single breakpoint break module clock generator module system integration module programmable timebase module monitor module serial peripheral 2-channel timer interface module 2 dual voltage low-voltage inhibit module 8-bit keyboard arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers user rom user ram monitor rom user rom vector space single external interrupt module porta ddra ddrc portc ddrd portd ddre porte internal bus osc1 osc2 cgmxfc rst (3) irq (3) interface module interrupt module computer operating properly module pta7/kbd7 ? ptb7/ad7 ptb6/ad6 ptb5/ad5 ptb4/ad4 ptb3/ad3 ptb2/ad2 ptb1/ad1 ptb0/ad0 v ddad /v refh 8-bit analog-to-digital converter module ptc6 (1) ptc5 (1) ptc4 (1, 2) ptc3 (1, 2) ptc2 (1, 2) ptc1 (1, 2) ptc0 (1, 2) ptd7/t2ch1 (1) ptd6/t2ch0 (1) ptd5/t1ch1 (1) ptd4/t1ch0 (1) ptd3/spsck (1) ptd2/mosi (1) ptd1/miso (1) ptd0/ss (1) pte1/rxd pte0/txd v ssad /v refl 2-channel timer interface module 1 32-khz oscillator phase-locked loop serial communications interface module power-on reset module memory map module mask option register 1 module security module mask option register 2 module power v ss v dd v ssa v dda 1. ports are software configurable with pullup device if input port. 2. higher current drive port pins 3. pin contains int egrated pullup device ddrb portb 64 bytes pta0/kbd0 (1) mc68hc08gp32a ? 32,256 bytes 512 bytes 307 bytes 36 bytes mc68hc08gp16a ? 15,872 bytes
general description mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 22 freescale semiconductor 1.5 pin assignments pin assignments are shown in figure 1-2 and figure 1-3 . note that the text in parentheses next to a signal in figure 1-2 indicates the module which uses the signal. figure 1-2. 42-pin sdip pin assignments 21 22 ptd5/t1ch1 ptd4/t1ch0 ptb1/ad1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 ptb0/ad0 ptd7/t2ch1 v ss ptd3/spsck ptd2/mosi rst irq ptd0/ss ptd1/miso pta0/kbd0 pta1/kbd1 pta2/kbd2 pta3/kbd3 pta4/kbd4 pta5/kbd5 pta6/kbd6 pta7/kbd7 ptb6/ad6 ptb7/ad7 ptb3/ad3 ptb4/ad4 ptb5/ad5 v ssa (pll) v dda (pll) v ddad /v refh (adc) v ssad /v refl (adc) cgmxfc (pll) osc2 osc1 ptc0 ptc1 ptc2 ptc3 ptc4 pte0/txd pte1/rxd ptb2/ad2 20 23 ptd6/t2ch0 v dd
pin assignments mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 23 figure 1-3. 44-pin qfp pin assignments 44 34 43 42 41 40 39 38 37 36 35 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 22 33 32 31 30 29 28 27 26 25 24 12 23 rst pte0/txd pte1/rxd irq ptc0 ptc1 ptc2 ptc3 ptc4 ptc5 ptc6 ptd5/t1ch1 ptd4/t1ch0 v dd v ss ptd3/spsck ptd2/mosi ptd1/miso ptd0/ss ptd6/t2ch0 ptd7/t2ch1 ptb0/ad0 ptb6/ad6 ptb7/ad7 v ddad /v refh v ssad /v refl pta0/kbd0 ptb2/ad2 ptb3/ad3 ptb1/ad1 ptb4/ad4 ptb5/ad5 pta4/kbd4 pta5/kbd5 v dda osc1 osc2 cgmxfc v ssa pta1/kbd1 pta6/kbd6 pta7/kbd7 pta3/kbd3 pta2/kbd2
general description mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 24 freescale semiconductor 1.6 pin functions descriptions of the pin functions are provided here. 1.6.1 power supply pins (v dd and v ss ) v dd and v ss are the power supply and ground pins. th e mcu operates from a single power supply. fast signal transitions on mcu pins place high, short-duration current demands on the power supply. to prevent noise problems, take special care to provide power supply bypassing at the mcu as figure 1-4 shows. place the c1 bypass capacitor as close to the mcu as possible. use a high-frequency-response ceramic capacitor for c1. c2 is an optional bulk current bypass capacitor for use in applications that require the port pins to source high current levels. figure 1-4. power supply bypassing 1.6.2 oscillator pins (osc1 and osc2) the osc1 and osc2 pins are the connections for the on-chip oscillator circuit. see chapter 4 clock generator module (cgm) . 1.6.3 external reset pin (rst ) a low on the rst pin forces the mcu to a known startup state. rst is bidirectional, allowing a reset of the entire system. it is driven low when any internal rese t source is asserted. this pin contains an internal pullup resistor. see chapter 15 system integration module (sim) . 1.6.4 external interrupt pin (irq ) irq is an asynchronous external interrupt pin. th is pin contains an internal pullup resistor. see chapter 7 external interrupt (irq) mcu v dd c2 c1 0.1 f v ss v dd + note: component values shown represent typical applications.
pin functions mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 25 1.6.5 cgm power supply pins (v dda and v ssa ) v dda and v ssa are the power supply pins for the analog portion of the clock generator module (cgm). connect the v dda pin to the same voltage potential as v dd , and the v ssa pin to the same voltage potential as v ss . decoupling of these pins should be as per the digital supply. see chapter 4 clock generator module (cgm) 1.6.6 external filter capacitor pin (cgmxfc) cgmxfc is an external filter c apacitor connection for the cgm. see chapter 4 clock generator module (cgm) 1.6.7 adc power supply/reference pins (v ddad /v refh and v ssad /v refl ) v ddad and v ssad are the power supply pins for the analog- to-digital converter (adc). connect the v ddad pin to the same voltage potential as v dd , and the v ssad pin to the same voltage potential as v ss . decoupling of these pi ns should be as per the digital supply. see chapter 3 analog-to-digital converter (adc) . v refh is the high reference supply for the adc, and is internally connected to v ddad . v refl is the low reference supply for the adc, and is internally connected to v ssad . 1.6.8 port a input/out put (i/o) pins (pta7/kbd7 ?pta0/kbd0 ) pta7?pta0 are general-purpose, bidirectional i/o port pins. any or all of the port a pins can be programmed to serve as keyboard interrupt pins. see chapter 12 input/output (i/o) ports and chapter 8 keyboard interrupt (kbi) module . these port pins also have selectable pullups when configured for input mode. the pullups are disengaged when configured for output mode. the pullups are selectable on an individual port bit basis. 1.6.9 port b i/o pi ns (ptb7/ad7?ptb0/ad0) ptb7?ptb0 are general-purpose, bidirectional i/o por t pins that can also be used for analog-to-digital converter (adc) inputs. see chapter 12 input/output (i/o) ports and chapter 3 analog-to-digital converter (adc) . 1.6.10 port c i /o pins (ptc6?ptc0) ptc6?ptc0 are general-purpose, bidirectional i/o port pins. see chapter 12 input/output (i/o) ports . ptc5 and ptc6 are only available on 44-pin qfp package. these port pins also have selectable pullups when configured for input mode. the pullups are disengaged when configured for output mode. the pullups are selectable on an individual port bit basis. 1.6.11 port d i/o pins (ptd7/t2ch1?ptd0/ss ) ptd7?ptd0 are special-function, bidirectional i/o port pins. ptd0?ptd3 can be programmed to be serial peripheral interface (spi) pins, while ptd4?ptd7 can be indi vidually programmed to be timer interface module (tim1 and tim2) pins. see chapter 18 timer interface modules (tim1 and tim2) , chapter 16 serial peripheral interface (spi) module , and chapter 12 input/output (i/o) ports .
general description mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 26 freescale semiconductor these port pins also have selectable pullups when configured for input mode. the pullups are disengaged when configured for output mode. the pullups are selectable on an individual port bit basis. 1.6.12 port e i/o pi ns (pte1/rxd?pte0/txd) pte0?pte1 are general-purpose, bidirectional i/o port pins. these pins can also be programmed to be serial communications interface (sci) pins. see chapter 14 serial communi cations interface (sci) module and chapter 12 input/output (i/o) ports .
mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 27 chapter 2 memory 2.1 introduction the cpu08 can address 64 kbytes of memory space. the memory map, shown in figure 2-1 , includes: 32,256 bytes user read-only memory (rom) for mc68hc08gp32a 15,872 bytes rom for mc68hc08gp16a 512 bytes of random-access memory (ram) 36 bytes of user-defined vectors 307 bytes of monitor rom 2.2 unimplemented memory locations accessing an unimplemented location can cause an illegal address reset. in the memory map ( figure 2-1 ) and in register figures in this document, unimplemented locations are shaded. 2.3 reserved memory locations accessing a reserved location can have unpredictable effects on mcu operation. in the figure 2-1 and in register figures in this document, reserved loca tions are marked with the word reserved or with the letter r. 2.4 input/output (i/o) section most of the control, status, and data registers ar e in the zero page area of $0000?$003f. additional i/o registers have these addresses: $fe00; sim break status register, sbsr $fe01; sim reset status register, srsr $fe03; sim break flag control register, sbfcr $fe04; interrupt status register 1, int1 $fe05; interrupt status register 2, int2 $fe06; interrupt status register 3, int3 $fe09; break address register high, brkh $fe0a; break address register low, brkl $fe0b; break status and control register, brkscr $fe0c; lvi status register, lvisr $ffff; cop control register, copctl data registers are shown in figure 2-2 . table 2-1 is a list of vector locations.
memory mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 28 freescale semiconductor $0000 $003f i/o registers 64 bytes $0040 $023f ram 512 bytes $0240 $7fff unimplemented 32,192 bytes $8000 $fdff rom 32,256 bytes reserved 16,384 bytes $8000 $bfff rom 15,872 bytes $c000 $fdff $fe00 sim break status register (sbsr) mc68hc08gp16a memory map $fe01 sim reset status register (srsr) $fe02 reserved (subar) $fe03 sim break flag control register (sbfcr) $fe04 interrupt status register 1 (int1) $fe05 interrupt status register 2 (int2) $fe06 interrupt status register 3 (int3) $fe07 reserved $fe08 reserved $fe09 break address register high (brkh) $fe0a break address register low (brkl) $fe0b break status and control register (brkscr) $fe0c lvi status register (lvisr) $fe0d $fe0f unimplemented 3 bytes $fe10 $fe1f reserved for compatibility with monitor code $fe20 $ff52 monitor rom (reserved for device testing only) 307 bytes $ff53 $ff7d unimplemented 43 bytes $ff7e reserved $ff7f $ffdb unimplemented 93 bytes $ffdc $ffff rom vectors 36 bytes note:$fff6?$fffd reserved for eight security bytes mc68hc08gp32a memory map figure 2-1. memory map
input/output (i/o) section mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 29 addr.register name bit 7654321bit 0 $0000 port a data register (pta) see page 110. read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 port b data register (ptb) see page 112. read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset $0002 port c data register (ptc) see page 114. read: 0 ptc6 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 write: reset: unaffected by reset $0003 port d data register (ptd) see page 116. read: ptd7 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset: unaffected by reset $0004 data direction register a (ddra) see page 110. read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 $0005 data direction register b (ddrb) see page 113. read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 $0006 data direction register c (ddrc) see page 114. read: 0 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset:00000000 $0007 data direction register d (ddrd) see page 120. read: ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset:00000000 $0008 port e data register (pte) see page 119. read:000000 pte1 pte0 write: reset: unaffected by reset $0009 $000b unimplemented read: write: reset:00000000 $000c data direction register e (ddre) see page 120. read:000000 ddre1 ddre0 write: reset:00000000 = unimplemented r = reserved u = unaffected figure 2-2. control, status, and data registers (sheet 1 of 7)
memory mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 30 freescale semiconductor $000d port a input pullup enable register (ptapue) see page 112. read: ptapue7 ptapue6 ptapue5 ptapue4 ptapue3 ptapue2 ptapue1 ptapue0 write: reset:00000000 $000e port c input pullup enable register (ptcpue) see page 116. read: 0 ptcpue6 ptcpue5 ptcpue4 ptcpue3 ptcpue2 ptcpue1 ptcpue0 write: reset:00000000 $000f port d input pullup enable register (ptdpue) see page 119. read: ptdpue7 ptdpue6 ptdpue5 ptdpue4 ptdpue3 ptdpue2 ptdpue1 ptdpue0 write: reset:00000000 $0010 spi control register (spcr) see page 195. read: sprie r spmstr cpol cpha spwom spe sptie write: reset:00101000 $0011 spi status and control register (spscr) see page 196. read: sprf errie ovrf modf spte modfen spr1 spr0 write: reset:00001000 $0012 spi data register (spdr) see page 198. read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset $0013 sci control register 1 (scc1) see page 150. read: loops ensci txinv m wake ilty pen pty write: reset:00000000 $0014 sci control register 2 (scc2) see page 152. read: sctie tcie scrie ilie te re rwu sbk write: reset:00000000 $0015 sci control register 3 (scc3) see page 154. read: r8 t8 r r orie neie feie peie write: reset:uu000000 $0016 sci status register 1 (scs1) see page 155. read: scte tc scrf idle or nf fe pe write: reset:11000000 $0017 sci status register 2 (scs2) see page 157. read: bkf rpf write: reset:00000000 $0018 sci data register (scdr) see page 158. read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-2. control, status, and data registers (sheet 2 of 7)
input/output (i/o) section mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 31 $0019 sci baud rate register (scbr) see page 158. read: scp1 scp0 r scr2 scr1 scr0 write: reset:00000000 $001a keyboard status and control register (intkbscr) see page 92. read:0000keyf0 imaskk modek write: ackk reset:00000000 $001b keyboard interrupt enable register (intkbier) see page 92. read: kbie7 kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 $001c timebase module control register (tbcr) see page 202. read: tbif tbr2 tbr1 tbr0 0 tbie tbon r write: tack reset:00000000 $001d irq status and control register (intscr) see page 86. read:0000irqf0 imask mode write: ack reset:00000000 $001e mask option register 2 (mor2) see page 103. read:00000 tbm- clksel osc- stopenb scibdsrc write: reset: mask defined $001f mask option register 1 (mor1) see page 104. read: coprs lvistop lvirstd lvipwrd lvi5or3 ssrec stop copd write: reset: mask defined $0020 timer 1 status and control register (t1sc) see page 213. read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 $0021 timer 1 counter register high (t1cnth) see page 214. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $0022 timer 1 counter register low (t1cntl) see page 214. read:bit 7654321bit 0 write: reset:00000000 $0023 timer 1 counter modulo register high (t1modh) see page 215. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-2. control, status, and data registers (sheet 3 of 7)
memory mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 32 freescale semiconductor $0024 timer 1 counter modulo register low (t1modl) see page 215. read: bit 7654321bit 0 write: reset:11111111 $0025 timer 1 channel 0 status and control register (t1sc0) see page 215. read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0026 timer 1 channel 0 register high (t1ch0h) see page 218. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0027 timer 1 channel 0 register low (t1ch0l) see page 218. read: bit 7654321bit 0 write: reset: indeterminate after reset $0028 timer 1 channel 1 status and control register (t1sc1) see page 215. read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 $0029 timer 1 channel 1 register high (t1ch1h) see page 218. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $002a timer 1 channel 1 register low (t1ch1l) see page 218. read: bit 7654321bit 0 write: reset: indeterminate after reset $002b timer 2 status and control register (t2sc) see page 213. read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 $002c timer 2 counter register high (t2cnth) see page 214. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $002d timer 2 counter register low (t2cntl) see page 214. read:bit 7654321bit 0 write: reset:00000000 $002e timer 2 counter modulo register high (t2modh) see page 215. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 $002f timer 2 counter modulo register low (t2modl) see page 215. read: bit 7654321bit 0 write: reset:11111111 addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-2. control, status, and data registers (sheet 4 of 7)
input/output (i/o) section mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 33 $0030 timer 2 channel 0 status and control register (t2sc0) see page 215. read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0031 timer 2 channel 0 register high (t2ch0h) see page 218. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0032 timer 2 channel 0 register low (t2ch0l) see page 218. read: bit 7654321bit 0 write: reset: indeterminate after reset $0033 timer 2 channel 1 status and control register (t2sc1) see page 215. read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 $0034 timer 2 channel 1 register high (t2ch1h) see page 218. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0035 timer 2 channel 1 register low (t2ch1l) see page 218. read: bit 7654321bit 0 write: reset: indeterminate after reset $0036 pll control register (pctl) see page 59. read: pllie pllf pllon bcs pre1 pre0 vpr1 vpr0 write: reset:00100000 $0037 pll bandwidth control register (pbwc) see page 61. read: auto lock acq 0000 r write: reset:00000000 $0038 pll multiplier select high register (pmsh) see page 61. read:0000 mul11 mul10 mul9 mul8 write: reset:00000000 $0039 pll multiplier select low register (pmsl) see page 62. read: mul7 mul6 mul5 mul4 mul3 mul2 mul1 mul0 write: reset:01000000 $003a pll vco range select register (pmrs) see page 62. read: vrs7 vrs6 vrs5 vrs4 vrs3 vrs2 vrs1 vrs0 write: reset:01000000 $003b pll reference divider select register (pmds) see page 63. read:0000 rds3 rds2 rds1 rds0 write: reset:00000001 addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-2. control, status, and data registers (sheet 5 of 7)
memory mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 34 freescale semiconductor $003c analog-to-digital status and control register (adscr) see page 43. read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: reset:00011111 $003d analog-to-digital data register (adr) see page 45. read:ad7ad6ad5ad4ad3ad2ad1ad0 write: reset:00000000 $003e analog-to-digital clock register (adclk) see page 45. read: adiv2 adiv1 adiv0 adiclk 0000 write: reset:00000000 $003f unimplemented read: write: reset: $fe00 sim break status register (sbsr) see page 175. read: rrrrrr sbsw r write: note reset: 0 note: writing a 0 clears sbsw. $fe01 sim reset status register (srsr) see page 176. read: por pin cop ilop ilad 0 lvi 0 write: por:10000000 $fe02 reserved read: rrrrrrrr write: reset: $fe03 sim break flag control register (sbfcr) see page 177. read: bcferrrrrrr write: reset: 0 $fe04 interrupt status register 1 (int1) see page 133. read: if6 if5 if4 if3 if2 if1 0 0 write:rrrrrrrr reset:00000000 $fe05 interrupt status register 2 (int2) see page 134. read: if14 if13 if12 if11 if10 if9 if8 if7 write:rrrrrrrr reset:00000000 $fe06 interrupt status register 3 (int3) see page 134. read:000000if16if15 write:rrrrrrrr reset:00000000 addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-2. control, status, and data registers (sheet 6 of 7)
input/output (i/o) section mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 35 $fe07 $fe08 reserved read: rrrrrrrr write: reset:00000000 $fe09 break address register high (brkh) see page 222. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $fe0a break address register low (brkl) see page 222. read: bit 7654321bit 0 write: reset:00000000 $fe0b break status and control register (brkscr) see page 221. read: brke brka 000000 write: reset:00000000 $fe0c lvi status register (lvisr) see page 101. read:lviout0000000 write: reset:00000000 $ffff cop control register (copctl) see page 69. read: low byte of reset vector write: writing clears cop counter (any value) reset: unaffected by reset addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-2. control, status, and data registers (sheet 7 of 7)
memory mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 36 freescale semiconductor . table 2-1. vector addresses vector priority ve ctor address vector lowest if16 $ffdc timebase vector (high) $ffdd timebase vector (low) if15 $ffde adc conversion complete vector (high) $ffdf adc conversion complete vector (low) if14 $ffe0 keyboard vector (high) $ffe1 keyboard vector (low) if13 $ffe2 sci transmit vector (high) $ffe3 sci transmit vector (low) if12 $ffe4 sci receive vector (high) $ffe5 sci receive vector (low) if11 $ffe6 sci error vector (high) $ffe7 sci error vector (low) if10 $ffe8 spi transmit vector (high) $ffe9 spi transmit vector (low) if9 $ffea spi receive vector (high) $ffeb spi receive vector (low) if8 $ffec tim2 overflow vector (high) $ffed tim2 overflow vector (low) if7 $ffee tim2 channel 1 vector (high) $ffef tim2 channel 1 vector (low) if6 $fff0 tim2 channel 0 vector (high) $fff1 tim2 channel 0 vector (low) if5 $fff2 tim1 overflow vector (high) $fff3 tim1 overflow vector (low) if4 $fff4 tim1 channel 1 vector (high) $fff5 tim1 channel 1 vector (low) if3 $fff6 tim1 channel 0 vector (high) $fff7 tim1 channel 0 vector (low) if2 $fff8 pll vector (high) $fff9 pll vector (low) if1 $fffa irq vector (high) $fffb irq vector (low) ? $fffc swi vector (high) $fffd swi vector (low) ? $fffe reset vector (high) highest $ffff reset vector (low)
random-access memory (ram) mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 37 2.5 random-access memory (ram) addresses $0040 through $023f are ram locations. t he location of the stack ram is programmable. the 16-bit stack pointer allows the stack to be anywhere in the 64-kbyte memory space. note for correct operation, the stack pointer must point only to ram locations. within page zero are 192 bytes of ram. because the location of the stack ram is programmable, all page zero ram locations can be used for i/o control and us er data or code. when the stack pointer is moved from its reset location at $00ff out of page zero, direct addressing mode instru ctions can efficiently access all page zero ram locations. page zero ram, therefore, provides ideal locations for frequently accessed global variables. before processing an interrupt, the cpu uses five bytes of the stack to save the contents of the cpu registers. note for m6805 compatibility, the h register is not stacked. during a subroutine call, the cpu uses two bytes of the stack to store the return address. the stack pointer decrements during pushes and increments during pulls. note be careful when using nested subrouti nes. the cpu may overwrite data in the ram during a subroutine or during the interrupt stacking operation. 2.6 read-only memory (rom) the user rom consists of: mc68hc08gp32a ? 32,256 bytes mc68hc08gp16a ? 15,872 bytes the monitor rom and vectors are located from $fe20?$ff52. see figure 2-1 . thirty-six bytes, $ffdc?$ffff, are dedicated to user-defined reset and interrupt vectors. security has been incorporated to prevent external viewing of the rom contents. this feature ensures that customer-developed software remains proprietary. see 19.3.2 security .
memory mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 38 freescale semiconductor
mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 39 chapter 3 analog-to-digital converter (adc) 3.1 introduction this section describes the 8-bit analog-to-digital converter (adc). 3.2 features features of the adc module include: eight channels with multiplexed input linear successive approxi mation with monotonicity 8-bit resolution single or continuous conversion conversion complete flag or conversion complete interrupt selectable adc clock 3.3 functional description the adc provides eight pins for sampling external sources at pins ptb7/ad7?ptb0/ad0. an analog multiplexer allows the single adc converter to se lect one of eight adc channels as adc voltage in (v adin ). v adin is converted by the successive approximati on register-based analog-to-digital converter. when the conversion is completed, adc places the result in the adc data register and sets a flag or generates an interrupt. see figure 3-2 . 3.3.1 adc port i/o pins ptb7/ad7?ptb0/ad0 are general-purpose i/o (input/outpu t) pins that share with the adc channels. the channel select bits define which a dc channel/port pin will be used as the input signal. the adc overrides the port i/o logic by forcing that pin as input to the adc. the remaining adc channels/port pins are controlled by the port i/o logic and can be used as ge neral-purpose i/o. writes to the port register or ddr will not have any affect on the port pin that is selected by the adc. read of a port pin in use by the adc will return a 0.
analog-to-digital converter (adc) mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 40 freescale semiconductor figure 3-1. block diagram highlighting adc block and pins single breakpoint break module clock generator module system integration module programmable timebase module monitor module serial peripheral 2-channel timer interface module 2 dual voltage low-voltage inhibit module 8-bit keyboard arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers user rom user ram monitor rom user rom vector space single external interrupt module porta ddra ddrc portc ddrd portd ddre porte internal bus osc1 osc2 cgmxfc rst (3) irq (3) interface module interrupt module computer operating properly module pta7/kbd7 ? ptb7/ad7 ptb6/ad6 ptb5/ad5 ptb4/ad4 ptb3/ad3 ptb2/ad2 ptb1/ad1 ptb0/ad0 v ddad /v refh 8-bit analog-to-digital converter module ptc6 (1) ptc5 (1) ptc4 (1, 2) ptc3 (1, 2) ptc2 (1, 2) ptc1 (1, 2) ptc0 (1, 2) ptd7/t2ch1 (1) ptd6/t2ch0 (1) ptd5/t1ch1 (1) ptd4/t1ch0 (1) ptd3/spsck (1) ptd2/mosi (1) ptd1/miso (1) ptd0/ss (1) pte1/rxd pte0/txd v ssad /v refl 2-channel timer interface module 1 32-khz oscillator phase-locked loop serial communications interface module power-on reset module memory map module mask option register 1 module security module mask option register 2 module power v ss v dd v ssa v dda 1. ports are software configurable with pullup device if input port. 2. higher current drive port pins 3. pin contains int egrated pullup device ddrb portb 64 bytes pta0/kbd0 (1) mc68hc08gp32a ? 32,256 bytes 512 bytes 307 bytes 36 bytes mc68hc08gp16a ? 15,872 bytes
functional description mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 41 figure 3-2. adc block diagram 3.3.2 voltage conversion when the input voltage to the adc equals v refh , the adc converts the signal to $ff (full scale). if the input voltage equals v refl , the adc converts it to $00. input voltages between v refh and v refl are a straight-line linear conversion. note inside the adc module, the reference voltages v refh is connected to the adc analog power, v ddad ; and v refl is connected to the adc analog ground, v ssad . therefore, the adc input voltage should not exceed these analog supply voltages. connect the v ddad pin to the same voltage potential as the v dd pin, and connect the v ssad pin to the same voltage potential as the v ss pin. the v ddad pin should be routed carefully for maximum noise immunity. internal data bus read ddrbx write ddrbx reset write ptbx read ptbx ptbx ddrbx ptbx interrupt logic channel select adc clock generator conversion complete adc (v adin ) adc clock cgmxclk bus clock adch4?adch0 adc data register aien coco disable disable adc channel x adiv2?adiv0 adiclk voltage in
analog-to-digital converter (adc) mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 42 freescale semiconductor 3.3.3 conversion time conversion starts after a write to the adscr. o ne conversion will take between 16 and 17 adc clock cycles. the adivx and adiclk bits should be set to provide a 1-mhz adc clock frequency. 3.3.4 conversion in continuous conversion mode, the adc data register will be filled with new data after each conversion. data from the previous conversion will be over written whether that data has been read or not. conversions will continue until the adco bit is cleared. the coco bit is set after each conversion and will stay set until the next read of the adc data register. in single conversion mode, conversion begins with a write to t he adscr. only one conversion occurs between writes to the adscr. when a conversion is in process and the adscr is written, the current conversion data should be discarded to prevent an incorrect reading. 3.3.5 accuracy and precision the conversion process is monot onic and has no missing codes. 3.4 interrupts when the aien bit is set, the adc module is c apable of generating cpu interrupts after each adc conversion. a cpu interrupt is generated if the coco bi t is 0. the coco bit is not used as a conversion complete flag when interrupts are enabled. 3.5 low-power modes the wait and stop instruction can put the mcu in low power-consumption standby modes. 3.5.1 wait mode the adc continues normal operation du ring wait mode. any enabled cpu interrupt request from the adc can bring the mcu out of wait mode. if the adc is not required to bring the mcu out of wait mode, power down the adc by setting ad ch4?adch0 bits in the adc status and control register before executing the wait instruction. 3.5.2 stop mode the adc module is inactive after the execution of a stop instruction. any pending conversion is aborted. adc conversions resume when the mcu exits stop mode after an external interrupt. allow one conversion cycle to stabi lize the analog circuitry. 3.6 i/o signals the adc module has eight pins shared with port b, ptb7/ad7?ptb0/ad0. 16 to 17 adc cycles adc frequency conversion time = number of bus cycles = conversion time bus frequency
i/o registers mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 43 3.6.1 adc analog power pin (v ddad )/adc voltage refe rence high pin (v refh ) the adc analog portion uses v ddad as its power pin. connect the v ddad pin to the same voltage potential as v dd . external filtering may be necessary to ensure clean v ddad for good results. note for maximum noise immunity, route v ddad carefully and place bypass capacitors as close as possible to the package. 3.6.2 adc analog ground pin (v ssad )/adc voltage refe rence low pin (v refl ) the adc analog portion uses v ssad as its ground pin. connect the v ssad pin to the same voltage potential as v ss . note route v ssad cleanly to avoid any offset errors. 3.6.3 adc voltage in (v adin ) v adin is the input voltage signal from one of the eight adc channels to the adc module. 3.7 i/o registers these i/o registers control and monitor adc operation: adc status and control register (adscr) adc data register (adr) adc clock register (adclk) 3.7.1 adc status and control register function of the adc status and control register (adscr) is described here. coco ? conversions complete in non-interrupt mode (aien = 0), coco is a read-only bit that is set at the end of each conversion. coco will stay set until cleared by a read of the adc data register. reset clears this bit. in interrupt mode (aien = 1), coco is a read-only bit that is not set at the end of a conversion. it always reads as 0. 1 = conversion completed (aien = 0) 0 = conversion not completed (aien = 0) or cpu interrupt enabled (aien = 1) note the write function of the coco bit is reserved. when writing to the adscr register, always have a 0 in the coco bit position. address: $003c bit 7654321bit 0 read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: reset:00011111 figure 3-3. adc status and control register (adscr)
analog-to-digital converter (adc) mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 44 freescale semiconductor aien ? adc interrupt enable bit when this bit is set, an interrupt is generated at th e end of an adc conversion. the interrupt signal is cleared when the data register is read or the status/control register is written. reset clears the aien bit. 1 = adc interrupt enabled 0 = adc interrupt disabled adco ? adc continuous conversion bit when set, the adc will convert samples continuously and update the adr register at the end of each conversion. only one conversion is completed between writes to the adscr when this bit is cleared. reset clears the adco bit. 1 = continuous adc conversion 0 = one adc conversion adch4?adch0 ? adc channel select bits adch4?adch0 form a 5-bit field which is used to select one of 16 adc channels. only eight channels, ad7?ad0, are available on this mcu. the channels are detailed in table 3-1 . care should be taken when using a port pin as both an analog and digital input simultaneously to prevent switching noise from corrupting the analog signal. the adc subsystem is turned off when the channel select bits are all set to 1. this feature allows for reduced power consumption for the mcu when the adc is not being used. note recovery from the disabled state requi res one conversion cycle to stabilize. the voltage levels supplied from internal reference nodes, as specified in table 3-1 , are used to verify the operation of the adc converter both in production test and for user applications. table 3-1. mux channel select adch4 adch3 adch2 adch1 adch0 input select 00000 ptb0/ad0 00001 ptb1/ad1 00010 ptb2/ad2 00011 ptb3/ad3 00100 ptb4/ad4 00101 ptb5/ad5 00110 ptb6/ad6 00111 ptb7/ad7 01000 reserved 11100 11101 v refh 11110 v refl 1 1 1 1 1 adc power off note: if any unused channels are selected, the re sulting adc conversion will be unknown or reserved.
i/o registers mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 45 3.7.2 adc data register one 8-bit result register, adc data register (adr), is provided. this register is updated each time an adc conversion completes. 3.7.3 adc clock register the adc clock register (adclk) selects the clock frequency for the adc. adiv2?adiv0 ? adc clock prescaler bits adiv2?adiv0 form a 3-bit field which selects the divi de ratio used by the adc to generate the internal adc clock. table 3-2 shows the available clock configurat ions. the adc clock should be set to approximately 1 mhz. adiclk ? adc input clock select bit adiclk selects either the bus clock or cgmxclk as the input clock source to generate the internal adc clock. reset selects cgmxclk as the adc clock source. address: $003d bit 7654321bit 0 read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: reset:00000000 = unimplemented figure 3-4. adc data register (adr) address: $003e bit 7654321bit 0 read: adiv2 adiv1 adiv0 adiclk 0000 write: reset:00000000 = unimplemented figure 3-5. adc clock register (adclk) table 3-2. adc clock divide ratio adiv2 adiv1 adiv0 adc clock rate 0 0 0 adc input clock 1 0 0 1 adc input clock 2 0 1 0 adc input clock 4 0 1 1 adc input clock 8 1 x x adc input clock 16 x = don?t care
analog-to-digital converter (adc) mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 46 freescale semiconductor if the external clock (cgmxclk) is equal to or greater than 1 mhz, cgmxclk can be used as the clock source for the adc. if cgmxclk is less t han 1 mhz, use the pll-generated bus clock as the clock source. as long as the internal adc clock is at approximately 1 mhz, correct operation can be guaranteed. 1 = internal bus clock 0 = external clock (cgmxclk) adc input clock frequency adiv2 adiv0 ? ----------------------------------------------------------------------- 1 m h z =
mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 47 chapter 4 clock generator module (cgm) 4.1 introduction this section describes the clock generator modul e. the cgm generates the crystal clock signal, cgmxclk, which operates at the frequency of the cr ystal. the cgm also generates the base clock signal, cgmout, which is based on either the crysta l clock divided by two or the phase-locked loop (pll) clock, cgmvclk, divided by two. in user mode, cg mout is the clock from which the sim derives the system clocks, including the bus clock, which is at a frequency of cgmout/2. in monitor mode, ptc3 determines the bus clock. the pll is a fully f unctional frequency generator designed for use with low-frequency crystals. the pll can generate an 8-mhz bus frequency using a 32.768-khz crystal. 4.2 features features of the cgm include: phase-locked loop with output frequency in integer multiples of an integer dividend of the crystal reference low-frequency crystal operation with low-power operation and high-output frequency resolution programmable prescaler for power-of-two increases in frequency programmable hardware voltage-controlled oscillator (vco) for low-jitter operation automatic bandwidth control mode for low-jitter operation automatic frequency lock detector cpu interrupt on entry or exit from locked condition configuration register bit to allow oscillator operation during stop mode 4.3 functional description the cgm consists of three major submodules: crystal oscillator circuit ? the crystal oscillat or circuit generates the constant crystal frequency clock, cgmxclk. phase-locked loop (pll) ? the pll generates the programmable vco frequency clock, cgmvclk. base clock selector circuit ? this software-cont rolled circuit selects either cgmxclk divided by two or the vco clock, cgmvclk, divided by two as the base cl ock, cgmout. the sim derives the system clocks from ei ther cgmout or cgmxclk.
clock generator module (cgm) mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 48 freescale semiconductor figure 4-1. block diagram highlighting cgm block and pins single breakpoint break module clock generator module system integration module programmable timebase module monitor module serial peripheral 2-channel timer interface module 2 dual voltage low-voltage inhibit module 8-bit keyboard arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers user rom user ram monitor rom user rom vector space single external interrupt module porta ddra ddrc portc ddrd portd ddre porte internal bus osc1 osc2 cgmxfc rst (3) irq (3) interface module interrupt module computer operating properly module pta7/kbd7 ? ptb7/ad7 ptb6/ad6 ptb5/ad5 ptb4/ad4 ptb3/ad3 ptb2/ad2 ptb1/ad1 ptb0/ad0 v ddad /v refh 8-bit analog-to-digital converter module ptc6 (1) ptc5 (1) ptc4 (1, 2) ptc3 (1, 2) ptc2 (1, 2) ptc1 (1, 2) ptc0 (1, 2) ptd7/t2ch1 (1) ptd6/t2ch0 (1) ptd5/t1ch1 (1) ptd4/t1ch0 (1) ptd3/spsck (1) ptd2/mosi (1) ptd1/miso (1) ptd0/ss (1) pte1/rxd pte0/txd v ssad /v refl 2-channel timer interface module 1 32-khz oscillator phase-locked loop serial communications interface module power-on reset module memory map module mask option register 1 module security module mask option register 2 module power v ss v dd v ssa v dda 1. ports are software configurable with pullup device if input port. 2. higher current drive port pins 3. pin contains int egrated pullup device ddrb portb 64 bytes pta0/kbd0 (1) mc68hc08gp32a ? 32,256 bytes 512 bytes 307 bytes 36 bytes mc68hc08gp16a ? 15,872 bytes
functional description mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 49 figure 4-2 shows the structure of the cgm. figure 4-2. cgm block diagram bcs phase detector loop filter frequency divider voltage controlled oscillator automatic mode control lock detector clock cgmxclk cgmout cgmvdv cgmvclk simoscen (from sim) oscillator (osc) interrupt control cgmint cgmrdv pll analog 2 cgmrclk osc2 osc1 select circuit v dda cgmxfc v ssa lock auto acq vpr1?vpr0 pllie pllf mul11?mul0 reference divider vrs7?vrs0 frequency divider pre1?pre0 oscstopenb (from mor) (to: sim, timtb15a, adc) phase-locked loop (pll) (to sim) (to sim) rds3?rds0
clock generator module (cgm) mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 50 freescale semiconductor 4.3.1 crystal os cillator circuit the crystal oscillator circuit consists of an inverting am plifier and an external crystal. the osc1 pin is the input to the amplifier and the osc2 pin is the out put. the simoscen signal from the system integration module (sim) or the oscstopenb bit in the mask opti on register enable the crystal oscillator circuit. the cgmxclk signal is the output of the crystal oscillator circuit and runs at a rate equal to the crystal frequency. cgmxclk is then buffered to pr oduce cgmrclk, the pll reference clock. cgmxclk can be used by other modules which require precise timing for operation. the duty cycle of cgmxclk is not guaranteed to be 50% and depends on ex ternal factors, including the crystal and related external components. an externally generated clock also can feed the osc1 pin of the crystal oscillator circuit. connect the external clock to th e osc1 pin and let the osc2 pin float. 4.3.2 phase-locked loop circuit (pll) the pll is a frequency generator that can operate in either acquisition mode or tracking mode, depending on the accuracy of the output frequency. the pll can change between acquisition and tracking modes either automatically or manually. 4.3.3 pll circuits the pll consists of these circuits: voltage-controlled oscillator (vco) reference divider frequency prescaler modulo vco frequency divider phase detector loop filter lock detector the operating range of the vco is programmable for a wide range of frequencies and for maximum immunity to external noise, in cluding supply and cgm/xfc noise. the vco frequency is bound to a range from roughly one-half to twice the center-of-range frequency, f vrs . modulating the voltage on the cgm/xfc pin changes the frequency wi thin this range. by design, f vrs is equal to the nominal center-of-range frequency, f nom , (38.4 khz) times a linear factor, l, and a power-of-two factor, e, or (l 2 e )f nom . cgmrclk is the pll reference clock, a buffered ve rsion of cgmxclk. cgmrclk runs at a frequency, f rclk , and is fed to the pll through a programmabl e modulo reference divi der, which divides f rclk by a factor, r. the divider?s output is the final re ference clock, cgmrdv, running at a frequency, f rdv =f rclk /r. with an external crystal (30 khz?100 khz), always set r = 1 for specified performance. with an external high-frequency cl ock source, use r to divide the external frequency to between 30 khz and 100 khz. the vco?s output clock, cgmvclk, running at a frequency, f vclk , is fed back through a programmable prescale divider and a programmable modulo divi der. the prescaler divides the vco clock by a power-of-two factor p and the modulo divider reduces th e vco clock by a factor, n. the dividers? output is the vco feedback clock, cgmvdv, running at a frequency, f vdv =f vclk /(n 2 p ). (see 4.3.6 programming the pll for more information.)
functional description mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 51 the phase detector then compares the vco feedback cloc k, cgmvdv, with the final reference clock, cgmrdv. a correction pulse is generated based on the phase difference between the two signals. the loop filter then slightly alters the dc voltage on the external capacitor co nnected to cgmxfc based on the width and direction of the correction pulse. the fi lter can make fast or slow corrections depending on its mode, described in 4.3.4 acquisition and tracking modes . the value of the external capacitor and the reference frequency determine the speed of th e corrections and the stability of the pll. the lock detector compares the frequencies of the vco feedback clock, cgmvdv, and the final reference clock, cgmrdv. therefore, the speed of the lock detector is directly proportional to the final reference frequency, f rdv . the circuit determines the mode of th e pll and the lock condition based on this comparison. 4.3.4 acquisition and tracking modes the pll filter is manually or automatically configurable into one of two operating modes: acquisition mode ? in acquisition mode, the filt er can make large frequency corrections to the vco. this mode is used at pll startup or when the pll has suffered a severe noise hit and the vco frequency is far off the desired freq uency. when in acquisition mode, the acq bit is clear in the pll bandwidth control register. (see 4.5.2 pll bandwidth control register .) tracking mode ? in tracking mode, the filter makes only small corrections to the frequency of the vco. pll jitter is much lower in tracking mode, but the response to noise is also slower. the pll enters tracking mode when the vco frequency is nearly correct, such as when the pll is selected as the base clock source. (see 4.3.8 base clock selector circuit .) the pll is automatically in tracking mode when not in acqui sition mode or when the acq bit is set. 4.3.5 manual and automa tic pll bandwidth modes the pll can change the bandwidth or operational mode of the loop filter manua lly or automatically. automatic mode is recommended for most users. in automatic bandwidth control mode (auto = 1), th e lock detector automatically switches between acquisition and tracking modes. automatic bandwidth c ontrol mode also is used to determine when the vco clock, cgmvclk, is safe to use as th e source for the base clock, cgmout. (see 4.5.2 pll bandwidth control register .) if pll interrupts are enabled, the software can wait for a pll interrupt request and then check the lock bit. if interrupts are disabled, software can poll the lock bit continuously (during pll startup, usually ) or at periodic intervals. in either case, when the lock bit is set, the vco clock is safe to use as the source for the base clock. (see 4.3.8 base clock selector circuit .) if the vco is selected as the source for the base clock and the lock bit is clear, the pll has suffered a severe noise hit and the software must take appr opriate action, depending on the application. (see 4.6 interrupts for information and precautions on using interrupts.) the following conditions apply when the p ll is in automatic bandwidth control mode: the acq bit (see 4.5.2 pll bandwidth control register ) is a read-only indicator of the mode of the filter. (see 4.3.4 acquisition and tracking modes .) the acq bit is set when the vco frequency is within a certain tolerance and is cleared when the vco frequency is out of a certain tolerance. (see 4.8 acquisition/lock time specifications for more information.) the lock bit is a read-only indica tor of the locked state of the pll.
clock generator module (cgm) mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 52 freescale semiconductor the lock bit is set when the vco frequency is with in a certain tolerance and is cleared when the vco frequency is out of a certain tolerance. (see 4.8 acquisition/lock time specifications for more information.) cpu interrupts can occur if enabled (pllie = 1) when the pll?s lock c ondition changes, toggling the lock bit. (see 4.5.1 pll control register .) the pll also may operate in manual mode (auto = 0) . manual mode is used by systems that do not require an indicator of the lock condition for proper operation. such systems typically operate well below f busmax . the following conditions apply when in manual mode: acq is a writable control bit that controls the mode of the filter. before turning on the pll in manual mode, the acq bit must be clear. before entering tracking mode (acq = 1), software must wait a given time, t acq (see 4.8 acquisition/lock time specifications ), after turning on the pll by setting pllon in the pll control register (pctl). software must wait a given time, t al , after entering tracking mode before selecting the pll as the clock source to cgmout (bcs = 1). the lock bit is disabled. cpu interrupts from the cgm are disabled. 4.3.6 programming the pll the following procedure shows how to program the pll. note the round function in the following equations means that the real number should be rounded to the nearest integer number. 1. choose the desired bus frequency, f busdes . 2. calculate the desired vco frequency (f our times the desired bus frequency). 3. choose a practical pll (crystal) reference frequency, f rclk , and the reference clock divider, r. typically, the reference crystal is 32.768 khz and r = 1. frequency errors to the pll are corrected at a rate of f rclk /r. for stability and lock time reduction, this rate must be as fast as possible. the vco frequency must be an integer multiple of this rate. the relationship between the vco frequency, f vclk , and the reference frequency, f rclk , is p, the power of two multiplier, and n, the range multiplier, are integers. in cases where desired bus frequency has some tolerance, choose f rclk to a value determined either by other module requirements (such as modules which are clock ed by cgmxclk), cost requirements, or ideally, as high as the specified range allows. see chapter 20 electrical specifications . choose the reference divider, r = 1. after choosing n and p, the actual bus frequency can be determined using equation in 2 above. f vclkdes 4f busdes = f vclk 2 p n r ----------- f rclk () =
functional description mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 53 when the tolerance on the bus frequency is tight, choose f rclk to an integer divisor of f busdes , and r = 1. if f rclk cannot meet this requirement, use the following equation to solve for r with practical choices of f rclk , and choose the f rclk that gives the lowest r. 4. select a vco frequency multiplier, n. reduce n/r to the lowest possible r. 5. if n is < n max , use p = 0. if n > n max , choose p using this table: then recalculate n: 6. calculate and verify the adequacy of the vco and bus frequencies f vclk and f bus . 7. select the vco?s power-of-two range multiplier e, according to this table: 8. select a vco linear range multiplier, l, where f nom = 38.4 khz current n value p 0 1 2 3 frequency range e (1) 1. do not program e to a value of 3. 0 < f vclk < 8 mhz 0 8 mhz f vclk < 16 mhz 1 16 mhz f vclk < 32 mhz 2 r round r max f vclkdes f rclk -------------------------- ?? ?? ?? integer f vclkdes f rclk -------------------------- ?? ?? ?? ? ?? ?? ?? = n round rf vclkdes f rclk ------------------------------------ - ?? ?? ?? = 0n clock generator module (cgm) mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 54 freescale semiconductor 9. calculate and verify the adequacy of the vco programmed center-of-range frequency, f vrs . the center-of-range frequency is the midpoint between the minimum and maximum frequencies attainable by the pll. for proper operation, 10. verify the choice of p, r, n, e, and l by comparing f vclk to f vrs and f vclkdes . for proper operation, f vclk must be within the application?s tolerance of f vclkdes , and f vrs must be as close as possible to f vclk . note exceeding the recommended maximum bus frequency or vco frequency can crash the mcu. 11. program the pll registers accordingly: a. in the pre bits of the pll control register (pctl), program the binary equivalent of p. b. in the vpr bits of the pll control register (pctl), program the binary equivalent of e. c. in the pll multiplier select register low (p msl) and the pll multiplier select register high (pmsh), program the binary equivalent of n. d. in the pll vco range select register (pmrs), program the binary coded equivalent of l. e. in the pll reference divider select register (pmds), program the binary coded equivalent of r. table 4-1 provides numeric exam ples (numbers are in hexadecimal notation): table 4-1. numeric example f bus f rclk rnpel 2.0 mhz 32.768 khz 1 f5 0 0 d1 2.4576 mhz 32.768 khz 1 12c 0 1 80 2.5 mhz 32.768 khz 1 132 0 1 83 4.0 mhz 32.768 khz 1 1e9 0 1 d1 4.9152 mhz 32.768 khz 1 258 0 2 80 5.0 mhz 32.768 khz 1 263 0 2 82 7.3728 mhz 32.768 khz 1 384 0 2 c0 8.0 mhz 32.768 khz 1 3d1 0 2 d0 f vrs l2 e () f nom = f vrs f vclk ? f nom 2 e 2 --------------------------
functional description mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 55 4.3.7 special programming exceptions the programming method described in 4.3.6 programming the pll does not account for three possible exceptions. a value of 0 for r, n, or l is meaningless when used in the equations given. to account for these exceptions: a 0 value for r or n is interpreted exactly the same as a value of 1. a 0 value for l disables the pll and prevents it s selection as the source for the base clock. (see 4.3.8 base clock selector circuit .) 4.3.8 base clock se lector circuit this circuit is used to select either the crystal cl ock, cgmxclk, or the vco clock, cgmvclk, as the source of the base clock, cgmout. the two input cl ocks go through a transition c ontrol circuit that waits up to three cgmxclk cycles and three cgmvclk cycles to change from one clock source to the other. during this time, cgmout is held in stasis. the outpu t of the transition control circuit is then divided by two to correct the duty cycle. therefore, the bus cl ock frequency, which is one-half of the base clock frequency, is one-fourth the frequency of the selected clock (cgmxclk or cgmvclk). the bcs bit in the pll control register (pctl) selects which clock drives cgmout. the vco clock cannot be selected as the base clock source if the pll is not turned on. the pll cannot be turned off if the vco clock is selected. the pll cannot be turned on or off simultaneously with the selection or deselection of the vco clock. the vco clock also cannot be selected as the base clock source if the factor l is programmed to a 0. this value would set up a condition inconsistent with the operation of the pll, so that the pll would be disabled and the crysta l clock would be forced as the source of the base clock. 4.3.9 cgm exte rnal connections in its typical configuration, the cgm requires up to nine external components. five of these are for the crystal oscillator and two or four are for the pll. the crystal oscillator is normally connected in a pierce oscillator configuration, as shown in figure 4-3 . figure 4-3 shows only the logical representation of the internal components and may not represent actual circuitry. the oscillator configuration uses five components: crystal, x 1 fixed capacitor, c 1 tuning capacitor, c 2 (can also be a fixed capacitor) feedback resistor, r b series resistor, r s the series resistor (r s ) is included in the diagram to follow strict pierce oscillator guidelines. refer to the crystal manufacturer?s data for more info rmation regarding values for c1 and c2. figure 4-3 also shows the external components for the pll: bypass capacitor, c byp filter network routing should be done with great care to minimize signal cross talk and noise. see 20.16 clock generation module characteristics for capacitor and resistor values.
clock generator module (cgm) mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 56 freescale semiconductor figure 4-3. cgm external connections 4.4 i/o signals the following paragraphs de scribe the cgm i/o signals. 4.4.1 crystal amplifi er input pin (osc1) the osc1 pin is an input to the crystal oscillator amplifier. 4.4.2 crystal amplifi er output pin (osc2) the osc2 pin is the output of the cr ystal oscillator inverting amplifier. 4.4.3 external filter capacitor pin (cgmxfc) the cgmxfc pin is required by the loop filter to filter out phase corrections. an external filter network is connected to this pin. (see figure 4-3 .) note to prevent noise problems, the filter network should be placed as close to the cgmxfc pin as possible, with minimum routing distances and no routing of other signals across the network. osc1 c1 c2 simoscen cgmxclk r b x1 r s c byp osc2 cgmxfc v dda note: filter network in box can be replaced with a signal capacitor, but will degrade stability. v dd oscstopenb (from config) r f1 c f2 c f1 v ssa
i/o signals mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 57 4.4.4 pll analog power pin (v dda ) v dda is a power pin used by the analog portions of the pll. connect the v dda pin to the same voltage potential as the v dd pin. note route v dda carefully for maximum noise immunity and place bypass capacitors as close as possible to the package. 4.4.5 pll analog ground pin (v ssa ) v ssa is a ground pin used by the analog portions of the pll. connect the v ssa pin to the same voltage potential as the v ss pin. note route v ssa carefully for maximum noise immunity and place bypass capacitors as close as possible to the package. 4.4.6 oscillator e nable signal (simoscen) the simoscen signal comes from the system integr ation module (sim) and enables the oscillator and pll. 4.4.7 oscillator stop mo de enable bit (oscstopenb) oscstopenb is a bit in the mask option register that enables the oscillator to continue operating during stop mode. if this bit is set, the oscillator continues running during stop mode. if this bit is not set, the oscillator is controlled by the simoscen signal which will disabl e the oscillator during stop mode. 4.4.8 crystal output frequency signal (cgmxclk) cgmxclk is the crystal oscillator output signal. it runs at the full speed of the crystal (f xclk ) and comes directly from the crys tal oscillator circuit. figure 4-3 shows only the logical relation of cgmxclk to osc1 and osc2 and may not represent the actual circui try. the duty cycle of cgmxclk is unknown and may depend on the crystal and other external factors. also, the frequency and amplitude of cgmxclk can be unstable at startup. 4.4.9 cgm base cl ock output (cgmout) cgmout is the clock output of the cgm. this signal goes to the sim, which generates the mcu clocks. cgmout is a 50 percent duty cycle clock running at twice the bus frequency. cgmout is software programmable to be either the oscillator output, cg mxclk, divided by two or the vco clock, cgmvclk, divided by two. 4.4.10 cgm cpu interrupt (cgmint) cgmint is the interrupt signal generated by the pll lock detector.
clock generator module (cgm) mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 58 freescale semiconductor 4.5 cgm registers these registers control and monitor operation of the cgm: pll control register (pctl) ? see 4.5.1 pll control register . pll bandwidth control register (pbwc) ? see 4.5.2 pll bandwidth control register . pll multiplier select register high (pmsh) ? see 4.5.3 pll multiplier select register high . pll multiplier select register low (pmsl) ? see 4.5.4 pll multiplier select register low . pll vco range select register (pmrs) ? see 4.5.5 pll vco range select register .) pll reference divider select register (pmds) ? see 4.5.6 pll reference divider select register . figure 4-4 is a summary of the cgm registers. addr.register name bit 7654321bit 0 $0036 pll control register (pctl) see page 59. read: pllie pllf pllon bcs pre1 pre0 vpr1 vpr0 write: reset:00100000 $0037 pll bandwidth control reg- ister (pbwc) see page 60. read: auto lock acq 0000 r write: reset:00000000 $0038 pll multiplier select high register (pmsh) see page 61. read:0000 mul11 mul10 mul9 mul8 write: reset:00000000 $0039 pll multiplier select low register (pmsl) see page 62. read: mul7 mul6 mul5 mul4 mul3 mul2 mul1 mul0 write: reset:01000000 $003a pll vco select range register (pmrs) see page 62. read: vrs7 vrs6 vrs5 vrs4 vrs3 vrs2 vrs1 vrs0 write: reset:01000000 $003b pll reference divider select register (pmds) see page 63. read:0000 rds3 rds2 rds1 rds0 write: reset:00000001 notes: 1. when auto = 0, pllie is forced clear and is read-only. 2. when auto = 0, pllf and lock read as clear. 3. when auto = 1, acq is read-only. 4. when pllon = 0 or vrs7:vrs0 = $0, bcs is forced clear and is read-only. 5. when pllon = 1, the pll programming register is read-only. 6. when bcs = 1, pllon is forced set and is read-only. = unimplemented r = reserved figure 4-4. cgm i/o register summary
cgm registers mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 59 4.5.1 pll control register the pll control register (pctl) contains the inte rrupt enable and flag bits, the on/off switch, the base clock selector bit, the prescaler bits, and the vco power-of-two range selector bits. pllie ? pll interrupt enable bit this read/write bit enables the pll to generate an interrupt request when the lock bit toggles, setting the pll flag, pllf. when the auto bit in the pll b andwidth control register (pbwc) is clear, pllie cannot be written and reads as 0. reset clears the pllie bit. 1 = pll interrupts enabled 0 = pll interrupts disabled pllf ? pll interrupt flag bit this read-only bit is set whenever the lock bit toggles. pllf generates an interrupt request if the pllie bit also is set. pllf always reads as 0 when the auto bit in the pll bandwidth control register (pbwc) is clear. clear the pllf bit by reading the pll control register. reset clears the pllf bit. 1 = change in lock condition 0 = no change in lock condition note do not inadvertently clear the pllf bit. any read or read-modify-write operation on the pll control register clears the pllf bit. pllon ? pll on bit this read/write bit activates the pll and enables the vco clock, cgmvclk. pllon cannot be cleared if the vco clock is driving t he base clock, cgmout (bcs = 1). (see 4.3.8 base clock selector circuit .) reset sets this bit so that the l oop can stabilize as the mcu is powering up. 1 = pll on 0 = pll off bcs ? base clock select bit this read/write bit selects either the crystal oscillator output, cgmxclk, or the vco clock, cgmvclk, as the source of the cgm output , cgmout. cgmout frequency is one-half the frequency of the selected clock. bcs cannot be set while the pllon bit is clear. after toggling bcs, it may take up to three cgmxclk and three cgmv clk cycles to complete the transition from one source clock to the other. during the transit ion, cgmout is held in stasis. (see 4.3.8 base clock selector circuit .) reset clears the bcs bit. 1 = cgmvclk divided by two drives cgmout 0 = cgmxclk divided by two drives cgmout note pllon and bcs have built-in protecti on that prevents the base clock selector circuit from selecting the vco clock as the source of the base clock if the pll is off. therefore, pllon cannot be cleared when bcs is set, and address: $0036 bit 7654321bit 0 read: pllie pllf pllon bcs pre1 pre0 vpr1 vpr0 write: reset:00100000 = unimplemented figure 4-5. pll control register (pctl)
clock generator module (cgm) mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 60 freescale semiconductor bcs cannot be set when pllon is cl ear. if the pll is off (pllon = 0), selecting cgmvclk requires two writes to the pll control register. (see 4.3.8 base clock selector circuit .) pre1 and pre0 ? prescaler program bits these read/write bits control a prescaler that selects the prescaler power-of-two multiplier, p. (see 4.3.3 pll circuits and 4.3.6 programming the pll .) pre1 and pre0 cannot be written when the pllon bit is set. reset clears these bits. note the value of p is normally 0 when using a 32.768-khz crystal as the reference. vpr1 and vpr0 ? vco power-of-two range select bits these read/write bits control the vco?s hardware power-of-two range multiplier e that, in conjunction with l (see 4.3.3 pll circuits , 4.3.6 programming the pll , and 4.5.5 pll vco range select register .) controls the hardware center-of-range frequency, f vrs . vpr1:vpr0 cannot be written when the pllon bit is set. reset clears these bits. 4.5.2 pll bandwidth control register the pll bandwidth control register (pbwc): selects automatic or manual (softw are-controlled) bandwidth control mode indicates when the pll is locked in automatic bandwidth control mode, indicates wh en the pll is in acquisition or tracking mode in manual operation, forces the pll into acquisition or tracking mode table 4-2. pre1 and pre0 programming pre1 and pre0 p prescaler multiplier 00 0 1 01 1 2 10 2 4 11 3 8 table 4-3. vpr1 and vpr0 programming vpr1 and vpr0 e vco power-of-two range multiplier 00 0 1 01 1 2 10 2 4 11 3 (1) 1. do not program e to a value of 3. 8
cgm registers mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 61 auto ? automatic bandwidth control bit this read/write bit selects automatic or manual b andwidth control. when initializing the pll for manual operation (auto = 0), clear the acq bit before turning on the pll. reset clears the auto bit. 1 = automatic bandwidth control 0 = manual bandwidth control lock ? lock indicator bit when the auto bit is set, lock is a read-only bit that becomes set when the vco clock, cgmvclk, is locked (running at the programmed frequency). wh en the auto bit is clear, lock reads as 0 and has no meaning. the write one function of this bit is reserved for test, so this bit must always be written a 0. reset clears the lock bit. 1 = vco frequency correct or locked 0 = vco frequency incorrect or unlocked acq ? acquisition mode bit when the auto bit is set, acq is a read-only bit that indicates whether the pll is in acquisition mode or tracking mode. when the auto bit is clear, acq is a read/write bit that controls whether the pll is in acquisition or tracking mode. in automatic bandwidth control mode (auto = 1), the last-written value from manual operation is stored in a temporary location and is recovered when manual operation resumes. reset clears this bit, enabling acquisition mode. 1 = tracking mode 0 = acquisition mode 4.5.3 pll multiplier select register high the pll multiplier select register high (pmsh) cont ains the programming informat ion for the high byte of the modulo feedback divider. mul11?mul8 ? multiplier select bits these read/write bits control the high byte of the modulo feedback divider that selects the vco frequency multiplier n. (see 4.3.3 pll circuits and 4.3.6 programming the pll .) a value of $0000 in address: $0037 bit 7654321bit 0 read: auto lock acq 0000 r write: reset:00000000 = unimplemented r = reserved figure 4-6. pll bandwidth control register (pbwc) address: $0038 bit 7654321bit 0 read:0000 mul11 mul10 mul9 mul8 write: reset:00000000 = unimplemented figure 4-7. pll multiplier select register high (pmsh)
clock generator module (cgm) mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 62 freescale semiconductor the multiplier select registers configures the m odulo feedback divider the same as a value of $0001. reset initializes the registers to $0040 for a default multiply value of 64. note the multiplier select bits have built-in protection such that they cannot be written when the pll is on (pllon = 1). pmsh[7:4] ? unimplemented bits these bits have no function and always read as 0s. 4.5.4 pll multiplier select register low the pll multiplier select register low (pmsl) contains the programming information for the low byte of the modulo feedback divider. mul7?mul0 ? multiplier select bits these read/write bits control the low byte of the modulo feedback divider that selects the vco frequency multiplier, n. (see 4.3.3 pll circuits and 4.3.6 programming the pll .) mul7?mul0 cannot be written when the pllon bit in the pctl is set. a value of $0000 in the multiplier select registers configures the modulo feedback divider the same as a value of $0001. reset initializes the register to $40 for a default multiply value of 64. note the multiplier select bits have built-in protection such that they cannot be written when the pll is on (pllon = 1). 4.5.5 pll vco range select register note pmrs may be called pvrs on other hc08 derivatives. the pll vco range select register (pmrs) contai ns the programming information required for the hardware configuration of the vco. address: $0038 bit 7654321bit 0 read: mul7 mul6 mul5 mul4 mul3 mul2 mul1 mul0 write: reset:01000000 figure 4-8. pll multiplier select register low (pmsl) address: $003a bit 7654321bit 0 read: vrs7 vrs6 vrs5 vrs4 vrs3 vrs2 vrs1 vrs0 write: reset:01000000 figure 4-9. pll vco range select register (pmrs)
cgm registers mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 63 vrs7?vrs0 ? vco range select bits these read/write bits control the hardware center-of -range linear multiplier l which, in conjunction with e (see 4.3.3 pll circuits , 4.3.6 programming the pll , and 4.5.1 pll control register ), controls the hardware center-of-range frequency, f vrs . vrs7?vrs0 cannot be written when the pllon bit in the pctl is set. (see 4.3.7 special programming exceptions .) a value of $00 in the vco range select register disables the pll and clears the bcs bi t in the pll control register (pctl). (see 4.3.8 base clock selector circuit and 4.3.7 special programming exceptions .) reset initializes the register to $40 for a default range multiply value of 64. note the vco range select bits have built-in protection such that they cannot be written when the pll is on (pllon = 1) and such that the vco clock cannot be selected as the source of the base clock (bcs = 1) if the vco range select bits are all clear. the pll vco range select register must be programmed correctly. incorrect programming can result in failure of the pll to achieve lock. 4.5.6 pll reference divi der select register note pmds may be called prds on other hc08 derivatives. the pll reference divider select register (pmds) contains the programming information for the modulo reference divider. rds3?rds0 ? reference divider select bits these read/write bits control the m odulo reference divider that selects the reference division factor, r. (see 4.3.3 pll circuits and 4.3.6 programming the pll .) rds7?rds0 cannot be written when the pllon bit in the pctl is set. a value of $00 in t he reference divider select register configures the reference divider the same as a value of $01. (see 4.3.7 special programming exceptions .) reset initializes the register to $01 for a default divide value of 1. note the reference divider select bits have built-in protection such that they cannot be written when the pll is on (pllon = 1). note the default divide value of 1 is recommended for all applications. pmds7?pmds4 ? unimplemented bits these bits have no function and always read as 0s. address: $003b bit 7654321bit 0 read:0000 rds3 rds2 rds1 rds0 write: reset:00000001 = unimplemented figure 4-10. pll reference divider select register (pmds)
clock generator module (cgm) mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 64 freescale semiconductor 4.6 interrupts when the auto bit is set in the pll bandwidth c ontrol register (pbwc), the pll can generate a cpu interrupt request every time the lock bit changes state. the pllie bit in the pll control register (pctl) enables cpu interrupts from the pll. pllf, the interrupt flag in the pctl, becomes set whether interrupts are enabled or not. when the auto bit is clear, cpu interrupts from the pll are disabled and pllf reads as 0. software should read the lock bit after a pll interrupt request to see if the request was due to an entry into lock or an exit from lock. when the pll enters lock, the vco clock, cgmvclk, divided by two can be selected as the cgmout source by setting bcs in the pctl. when the pll exits lock, the vco clock frequency is corrupt, and appropriate precautions s hould be taken. if the application is not frequency sensitive, interrupts should be disabled to prevent pll interrupt service routines from impeding software performance or from exceeding stack limitations. note software can select the cgmvclk divi ded by two as the cgmout source even if the pll is not locked (lock = 0). therefore, software should make sure the pll is locked before setting the bcs bit. 4.7 special modes the wait instruction puts the mcu in low power-consumption standby modes. 4.7.1 wait mode the wait instruction does not affect the cgm. before entering wait mode, software can disengage and turn off the pll by clearing the bcs and pllon bits in the pll control register (pctl) to save power. less power-sensitive applications can disengage the pll without turning it off, so that the pll clock is immediately available at wait exi t. this would be the case also when the pll is to wake the mcu from wait mode, such as when the pll is first enabled and waiting for lock or lock is lost. 4.7.2 stop mode if the oscstopenb bit in the mask option register is cleared, then the stop instruction disables the cgm (oscillator and phase locked loop) and hold s low all cgm outputs (cgmxclk, cgmout, and cgmint). if the stop instruction is executed with the vco cl ock, cgmvclk, divided by two driving cgmout, the pll automatically clears the bcs bit in the pll cont rol register (pctl), thereby selecting the crystal clock, cgmxclk, divided by two as the source of cgmout. when the mcu recovers from stop, the crystal clock divided by two drives cgmout and bcs remains clear. if the oscstopenb bit in the mask option register is set, then the phase locked loop is shut off but the oscillator will continue to operate in stop mode. 4.7.3 cgm during break interrupts the system integration module (sim) controls whethe r status bits in other modules can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bits during the break state. (see chapter 15 system integration module (sim) .)
acquisition/lock ti me specifications mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 65 to allow software to clear status bits during a break in terrupt, write a 1 to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect the pllf bit during the break state, write a 0 to the bcfe bit. with bcfe at 0 (its default state), software can read and write the pll control register during the break state without affecting the pllf bit. 4.8 acquisition/lock time specifications the acquisition and lock times of the pll are, in many applications, the most critical pll design parameters. proper design and use of the pll ensure s the highest stability and lowest acquisition/lock times. 4.8.1 acquisition/lock time definitions typical control systems refer to the acquisition time or lock time as the reaction time, within specified tolerances, of the system to a step input. in a pll, the step input occurs when the pll is turned on or when it suffers a noise hit. the tolerance is usually specified as a percentage of the step input or when the output settles to the desired value plus or minus a percentage of the frequency change. therefore, the reaction time is constant in this definition, r egardless of the size of the step input. for example, consider a system with a 5 percent acquisition time tolerance. if a command instructs the system to change from 0 hz to 1 mhz, the acquisition time is the time taken for the frequency to reach 1mhz 50 khz. fifty khz = 5% of the 1-mhz step input. if the system is operating at 1 mhz and suffers a ?100-khz noise hit, the acquisition time is the time taken to return from 900 khz to 1 mhz 5khz. five khz = 5% of the 100-khz step input. other systems refer to acquisition and lock times as t he time the system takes to reduce the error between the actual output and the desired output to within specified tolerances. therefore, the acquisition or lock time varies according to the original error in the output. minor errors may not even be registered. typical pll applications prefer to use this definition beca use the system requires the output frequency to be within a certain tolerance of the desired frequenc y regardless of the size of the initial error. 4.8.2 parametric in fluences on reaction time acquisition and lock times are designed to be as short as possible while still pr oviding the highest possible stability. these reaction times are not constant, however . many factors directly and indirectly affect the acquisition time. the most critical parameter which affects the reacti on times of the pll is the reference frequency, f rdv . this frequency is the input to the phase detector and controls how often the pll makes corrections. for stability, the corrections must be small compared to the desired frequency, so several corrections are required to reduce the frequency error. therefore, the slower the reference the longer it takes to make these corrections. this parameter is under user control via the choice of crystal frequency f xclk and the r value programmed in the reference divider. (see 4.3.3 pll circuits , 4.3.6 programming the pll , and 4.5.6 pll reference divider select register .) another critical parameter is the external filter ne twork. the pll modifies the voltage on the vco by adding or subtracting charge from capacitors in this network. therefore, the rate at which the voltage changes for a given frequency error (thus change in char ge) is proportional to the capacitance. the size of the capacitor also is related to the stability of the pll. if the capacitor is too small, the pll cannot make small enough adjustments to the voltage and the system c annot lock. if the capacitor is too large, the pll may not be able to adjust the voltage in a reasonable time. (see 4.8.3 choosing a filter .)
clock generator module (cgm) mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 66 freescale semiconductor also important is the operating voltage potential applied to v dda . the power supply potential alters the characteristics of the pll. a fixed value is best. va riable supplies, such as batteries, are acceptable if they vary within a known range at very slow sp eeds. noise on the power s upply is not acceptable, because it causes small frequency errors which continually change the acquisition time of the pll. temperature and processing also can affect acquisition time because the electrical characteristics of the pll change. the part operates as spec ified as long as thes e influences stay within the specified limits. external factors, however, can caus e drastic changes in the operation of the pll. these factors include noise injected into the pll through the filter capacito r, filter capacitor leakage, stray impedances on the circuit board, and even humidity or circuit board contamination. 4.8.3 choosing a filter as described in 4.8.2 parametric influences on reaction time , the external filter network is critical to the stability and reaction time of the pll. the pl l is also dependent on reference frequency and supply voltage. figure 4-11 shows two types of filter circuits. in low-cost applications, where stability and reaction time of the pll are not critical, the three component filter network of figure 4-11 (b) can be replaced by a single capacitor, c f , shown in figure 4-11 (a). refer to table 4-4 for recommended filter components at various reference frequencies. for reference frequencies between the values listed in the table, extrapolate to the nearest common capacitor value. in general, a slight ly larger capacitor provides more stability at the expense of increased lock time. figure 4-11. pll filter table 4-4. example filter component values f rclk c f1 c f2 r f1 c f 32 khz 0.15 f 15 nf 2 k 0.22 f 40 khz 0.12 f 12 nf 2 k 0.18 f 50 khz 0.10 f 10 nf 2 k 0.18 f 60 khz 82 nf 8.2 nf 2 k 0.12 f 70 khz 68 nf 6.8 nf 2 k 0.12 f 80 khz 56 nf 5.6 nf 2 k 0.1 f 90 khz 56 nf 5.6 nf 2 k 0.1 f 100 khz 47 nf 4.7 nf 2 k 82 nf cgmxfc r f1 c f2 c f1 v ssa cgmxfc c f v ssa (a) (b)
mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 67 chapter 5 computer operating properly (cop) 5.1 introduction the computer operating properly (cop) module cont ains a free-running counter that generates a reset if allowed to overflow. the cop modul e helps software recover from runaway code. prevent a cop reset by clearing the cop counter periodically. the cop m odule can be disabled through the copd bit in the mask option register. 5.2 functional description figure 5-1 shows the structure of the cop module. figure 5-1. cop block diagram copctl write cgmxclk reset circuit reset status register internal reset sources 12-bit sim counter clear all stages 6-bit cop counter cop disable reset copctl write clear cop module copen (from sim) cop counter cop clock cop timeout stop instruction (from mor) cop rate sel (from mor) clear stages 5?12
computer operating properly (cop) mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 68 freescale semiconductor the cop counter is a free-running 6-bit counter preceded by the 12-bit sim counter. if not cleared by software, the cop counter overflows and generates an asynchronous reset after 2 18 ?2 4 or 2 13 ?2 4 cgmxclk cycles, depending on the state of the cop rate select bit, coprs, in the mask option register. with a 2 13 ?2 4 cgmxclk cycle overflow option, a 32.768- khz crystal gives a cop timeout period of 250 ms. writing any value to location $ffff before an overflow occurs prevent s a cop reset by clearing the cop counter and stages 12 through 5 of the sim counter. note service the cop immediately after rese t and before entering or after exiting stop mode to guarantee the maximum time before the first cop counter overflow. a cop reset pulls the rst pin low for 32 cgmxclk cycles and sets the cop bit in the reset status register (rsr). in monitor mode, the cop is disabled if the rst pin or the irq is held at v tst . during the break state, v tst on the rst pin disables the cop. note place cop clearing instructions in the main program and not in an interrupt subroutine. such an interrupt s ubroutine could keep the cop from generating a reset even while the main program is not working properly. 5.3 i/o signals the following paragraphs describe the signals shown in figure 5-1 . 5.3.1 cgmxclk cgmxclk is the crystal oscillator output signal. cg mxclk frequency is equal to the crystal frequency. 5.3.2 stop instruction the stop instruction clears the sim counter. 5.3.3 copctl write writing any value to the cop control register (copctl) (see 5.4 cop control register ) clears the cop counter and clears stages 12 through 5 of the sim counter. reading the cop control register returns the low byte of the reset vector. 5.3.4 powe r-on reset the power-on reset (por) circuit clears the sim counter 4096 cgmxclk cycles after power-up. 5.3.5 internal reset an internal reset clears the sim counter and the cop counter. 5.3.6 copd (cop disable) the copd signal reflects the state of the cop dis able bit (copd) in the mask option register. see chapter 11 mask option registers (mor2 and mor1).
cop control register mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 69 5.3.7 coprs (cop rate select) the coprs signal reflects the state of the cop rate select bit (coprs) in the mask option register. see chapter 11 mask option registers (mor2 and mor1), 5.4 cop control register the cop control register is located at address $ffff and overlaps the reset vector. writing any value to $ffff clears the cop counter and starts a new timeout period. reading location $ffff returns the low byte of the reset vector. 5.5 interrupts the cop does not generate cpu interrupt requests. 5.6 monitor mode when monitor mode is entered with v tst on the irq pin, the cop is disabled as long as v tst remains on the irq pin or the rst pin. 5.7 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 5.7.1 wait mode the cop remains active during wait mode. if cop is enabled, a reset will occur at cop timeout. 5.7.2 stop mode stop mode turns off the cgmxclk input to the co p and clears the cop prescaler. service the cop immediately before entering or after exiting stop mode to ensure a full cop timeout period after entering or exiting stop mode. to prevent inadvertently turning off the cop with a stop instruction, a configuration option is available that disables the stop instruction. when the st op bit in the mask option register has the stop instruction is disabled, execution of a stop instruction results in an illegal opcode reset. 5.8 cop module during break mode the cop is disabled during a break interrupt when v tst is present on the rst pin. address: $ffff bit 7654321bit 0 read: low byte of reset vector write: clear cop counter reset: unaffected by reset figure 5-2. cop control register (copctl)
computer operating properly (cop) mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 70 freescale semiconductor
mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 71 chapter 6 central processor unit (cpu) 6.1 introduction the m68hc08 cpu (central processor unit) is an e nhanced and fully object-code- compatible version of the m68hc05 cpu. the cpu08 reference manual (document order number cpu08rm/ad) contains a description of the cpu instruction set, addressing modes, and architecture. 6.2 features features of the cpu include: object code fully upward-compatible with m68hc05 family 16-bit stack pointer with stack manipulation instructions 16-bit index register with x-re gister manipulation instructions 8-mhz cpu internal bus frequency 64-kbyte program/data memory space 16 addressing modes memory-to-memory data moves without using accumulator fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions enhanced binary-coded decimal (bcd) data handling modular architecture with expandable internal bus definition for extension of addressing range beyond 64 kbytes low-power stop and wait modes 6.3 cpu registers figure 6-1 shows the five cpu registers. cpu registers are not part of the memory map.
central processor unit (cpu) mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 72 freescale semiconductor figure 6-1. cpu registers 6.3.1 accumulator the accumulator is a general-purpose 8-bit register. the cpu uses the accumulator to hold operands and the results of arithmetic/logic operations. 6.3.2 index register the 16-bit index register allows i ndexed addressing of a 64-kbyte memory space. h is the upper byte of the index register, and x is the lower byte. h:x is the concatenated 16-bit index register. in the indexed addressing modes, th e cpu uses the contents of the index register to determine the conditional address of the operand. the index register can serve also as a temporary data storage location. bit 7654321bit 0 read: write: reset: unaffected by reset figure 6-2. accumulator (a) bit 151413121110987654321 bit 0 read: write: reset:00000000 xxxxxxxx x = indeterminate figure 6-3. index register (h:x) accumulator (a) index register (h:x) stack pointer (sp) program counter (pc) condition code register (ccr) carry/borrow flag zero flag negative flag interrupt mask half-carry flag two?s complement overflow flag v11hinzc h x 0 0 0 0 7 15 15 15 70
cpu registers mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 73 6.3.3 stack pointer the stack pointer is a 16-bit register that contains the address of the next location on the stack. during a reset, the stack pointer is preset to $00ff. the reset stack pointer (rsp) instruction sets the least significant byte to $ff and does not affect the most significant byte. the stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. in the stack pointer 8-bit offset and 16-bit offset a ddressing modes, the stack pointer can function as an index register to access data on t he stack. the cpu uses the contents of the stack pointer to determine the conditional address of the operand. note the location of the stack is arbitrary and may be relocated anywhere in random-access memory (ram). moving the sp out of page 0 ($0000 to $00ff) frees direct address (page 0) space. for correct operation, the stack pointer must point only to ram locations. 6.3.4 program counter the program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. normally, the program counter automatically increm ents to the next sequential memory location every time an instruction or operand is fetched. jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. during reset, the program counter is loaded with the reset vector address located at $fffe and $ffff. the vector address is the address of the first instruction to be executed after exiting the reset state. bit 151413121110987654321 bit 0 read: write: reset:0000000011111111 figure 6-4. stack pointer (sp) bit 151413121110987654321 bit 0 read: write: reset: loaded with vector from $fffe and $ffff figure 6-5. program counter (pc)
central processor unit (cpu) mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 74 freescale semiconductor 6.3.5 condition code register the 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. bits 6 and 5 are set per manently to 1. the following paragraphs describe the functions of the condition code register. v ? overflow flag the cpu sets the overflow flag when a two's complement overflow occurs. the signed branch instructions bgt, bge, ble, and blt use the overflow flag. 1 = overflow 0 = no overflow h ? half-carry flag the cpu sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add-without-carry (add) or add-with-carry (adc) operation. the half-carry flag is required for binary-coded decimal (bcd) arithmetic operations. th e daa instruction uses the states of the h and c flags to determine the appropriate correction factor. 1 = carry between bits 3 and 4 0 = no carry between bits 3 and 4 i ? interrupt mask when the interrupt mask is set, all maskable cp u interrupts are disabled. cpu interrupts are enabled when the interrupt mask is cleared. when a cpu interrupt occurs, the interrupt mask is set automatically after the cpu registers are saved on the stack, but before the interrupt vector is fetched. 1 = interrupts disabled 0 = interrupts enabled note to maintain m6805 family compatibil ity, the upper byte of the index register (h) is not stacked automatically. if the interrupt service routine modifies h, then the user must stack and unstack h using the pshh and pulh instructions. after the i bit is cleared, the highest-priori ty interrupt request is serviced first. a return-from-interrupt (rti) instruction pulls the cpu registers from the stack and restores the interrupt mask from the stack. after any reset, the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction (cli). n ? negative flag the cpu sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result. 1 = negative result 0 = non-negative result bit 7654321bit 0 read: v11hinzc write: reset:x11x1xxx x = indeterminate figure 6-6. condition code register (ccr)
arithmetic/logic unit (alu) mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 75 z ? zero flag the cpu sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = zero result 0 = non-zero result c ? carry/borrow flag the cpu sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. some instructions ? such as bit test and branch, shift, and rotate ? also clear or set the carry/borrow flag. 1 = carry out of bit 7 0 = no carry out of bit 7 6.4 arithmetic/logic unit (alu) the alu performs the arithmetic and logic operations defined by the instruction set. refer to the cpu08 reference manual (document order number cpu08rm/ad) for a description of the instructions and addressing modes and more detail about the architecture of the cpu. 6.5 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 6.5.1 wait mode the wait instruction: clears the interrupt mask (i bit) in the condition code register, enabling interrupts. after exit from wait mode by interrupt, the i bit remains cl ear. after exit by reset, the i bit is set. disables the cpu clock 6.5.2 stop mode the stop instruction: clears the interrupt mask (i bit) in the conditi on code register, enabling external interrupts. after exit from stop mode by external interrupt, the i bit remains clear. after exit by reset, the i bit is set. disables the cpu clock after exiting stop mode, the cpu clock begins ru nning after the oscillator stabilization delay. 6.6 cpu during break interrupts if a break module is present on the mcu, the cpu starts a break interrupt by: loading the instruction register with the swi instruction loading the program counter with $fffc:$fffd or with $fefc:$fefd in monitor mode the break interrupt begins after completion of the cpu instruction in progress. if the break address register match occurs on the last cycle of a cpu in struction, the break inte rrupt begins immediately. a return-from-interrupt instruction (rti) in the break routine ends the break interrupt and returns the mcu to normal operation if the break interrupt has been deasserted.
central processor unit (cpu) mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 76 freescale semiconductor 6.7 instruction set summary table 6-1 provides a summary of the m68hc08 instruction set. table 6-1. instruction set summary (sheet 1 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x adc opr ,sp adc opr ,sp add with carry a (a) + (m) + (c) ? imm dir ext ix2 ix1 ix sp1 sp2 a9 b9 c9 d9 e9 f9 9ee9 9ed9 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 add # opr add opr add opr add opr ,x add opr ,x add ,x add opr ,sp add opr ,sp add without carry a (a) + (m) ? imm dir ext ix2 ix1 ix sp1 sp2 ab bb cb db eb fb 9eeb 9edb ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ais # opr add immediate value (signed) to sp sp (sp) + (16 ? m) ??????imm a7 ii 2 aix # opr add immediate value (signed) to h:x h:x (h:x) + (16 ? m) ??????imm af ii 2 and # opr and opr and opr and opr ,x and opr ,x and ,x and opr ,sp and opr ,sp logical and a (a) & (m) 0 ? ? ? imm dir ext ix2 ix1 ix sp1 sp2 a4 b4 c4 d4 e4 f4 9ee4 9ed4 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 asl opr asla aslx asl opr ,x asl ,x asl opr ,sp arithmetic shift left (same as lsl) ?? dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 asr opr asra asrx asr opr ,x asr opr ,x asr opr ,sp arithmetic shift right ?? dir inh inh ix1 ix sp1 37 47 57 67 77 9e67 dd ff ff 4 1 1 4 3 5 bcc rel branch if carry bit clear pc (pc) + 2 + rel ? (c) = 0 ??????rel 24 rr 3 bclr n , opr clear bit n in m mn 0 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 bcs rel branch if carry bit set (same as blo) pc (pc) + 2 + rel ? (c) = 1 ??????rel 25 rr 3 beq rel branch if equal pc (pc) + 2 + rel ? (z) = 1 ??????rel 27 rr 3 bge opr branch if greater than or equal to (signed operands) pc (pc) + 2 + rel ? (n v ) = 0 ??????rel 90 rr 3 bgt opr branch if greater than (signed operands) pc (pc) + 2 + rel ? (z) | (n v ) = 0 ??????rel 92 rr 3 bhcc rel branch if half carry bit clear pc (pc) + 2 + rel ? (h) = 0 ??????rel 28 rr 3 bhcs rel branch if half carry bit set pc (pc) + 2 + rel ? (h) = 1 ??????rel 29 rr 3 bhi rel branch if higher pc (pc) + 2 + rel ? (c) | (z) = 0 ??????rel 22 rr 3 c b0 b7 0 b0 b7 c
instruction set summary mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 77 bhs rel branch if higher or same (same as bcc) pc (pc) + 2 + rel ? (c) = 0 ??????rel 24 rr 3 bih rel branch if irq pin high pc (pc) + 2 + rel ? irq = 1 ??????rel 2f rr 3 bil rel branch if irq pin low pc (pc) + 2 + rel ? irq = 0 ??????rel 2e rr 3 bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit opr ,sp bit opr ,sp bit test (a) & (m) 0 ? ? ? imm dir ext ix2 ix1 ix sp1 sp2 a5 b5 c5 d5 e5 f5 9ee5 9ed5 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ble opr branch if less than or equal to (signed operands) pc (pc) + 2 + rel ? (z) | (n v ) = 1 ??????rel 93 rr 3 blo rel branch if lower (same as bcs) pc (pc) + 2 + rel ? (c) = 1 ??????rel 25 rr 3 bls rel branch if lower or same pc (pc) + 2 + rel ? (c) | (z) = 1 ??????rel 23 rr 3 blt opr branch if less than (signed operands) pc (pc) + 2 + rel ? (n v ) = 1 ??????rel 91 rr 3 bmc rel branch if interrupt mask clear pc (pc) + 2 + rel ? (i) = 0 ??????rel 2c rr 3 bmi rel branch if minus pc (pc) + 2 + rel ? (n) = 1 ??????rel 2b rr 3 bms rel branch if interrupt mask set pc (pc) + 2 + rel ? (i) = 1 ??????rel 2d rr 3 bne rel branch if not equal pc (pc) + 2 + rel ? (z) = 0 ??????rel 26 rr 3 bpl rel branch if plus pc (pc) + 2 + rel ? (n) = 0 ??????rel 2a rr 3 bra rel branch always pc (pc) + 2 + rel ??????rel 20 rr 3 brclr n , opr , rel branch if bit n in m clear pc (pc) + 3 + rel ? (mn) = 0 ????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc (pc) + 2 ??????rel 21 rr 3 brset n , opr , rel branch if bit n in m set pc (pc) + 3 + rel ? (mn) = 1 ????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 bset n , opr set bit n in m mn 1 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 bsr rel branch to subroutine pc (pc) + 2; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1 pc (pc) + rel ??????rel ad rr 4 cbeq opr,rel cbeqa # opr,rel cbeqx # opr,rel cbeq opr, x+ ,rel cbeq x+ ,rel cbeq opr, sp ,rel compare and branch if equal pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 3 + rel ? (x) ? (m) = $00 pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 2 + rel ? (a) ? (m) = $00 pc (pc) + 4 + rel ? (a) ? (m) = $00 ?????? dir imm imm ix1+ ix+ sp1 31 41 51 61 71 9e61 dd rr ii rr ii rr ff rr rr ff rr 5 4 4 5 4 6 clc clear carry bit c 0 ?????0inh 98 1 cli clear interrupt mask i 0 ??0???inh 9a 2 table 6-1. instruction set summary (sheet 2 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc
central processor unit (cpu) mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 78 freescale semiconductor clr opr clra clrx clrh clr opr ,x clr ,x clr opr ,sp clear m $00 a $00 x $00 h $00 m $00 m $00 m $00 0??01? dir inh inh inh ix1 ix sp1 3f 4f 5f 8c 6f 7f 9e6f dd ff ff 3 1 1 1 3 2 4 cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x cmp opr ,sp cmp opr ,sp compare a with m (a) ? (m) ?? imm dir ext ix2 ix1 ix sp1 sp2 a1 b1 c1 d1 e1 f1 9ee1 9ed1 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 com opr coma comx com opr ,x com ,x com opr ,sp complement (one?s complement) m (m ) = $ff ? (m) a (a ) = $ff ? (m) x (x ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) 0?? 1 dir inh inh ix1 ix sp1 33 43 53 63 73 9e63 dd ff ff 4 1 1 4 3 5 cphx # opr cphx opr compare h:x with m (h:x) ? (m:m + 1) ?? imm dir 65 75 ii ii+1 dd 3 4 cpx # opr cpx opr cpx opr cpx ,x cpx opr ,x cpx opr ,x cpx opr ,sp cpx opr ,sp compare x with m (x) ? (m) ?? imm dir ext ix2 ix1 ix sp1 sp2 a3 b3 c3 d3 e3 f3 9ee3 9ed3 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 daa decimal adjust a (a) 10 u?? inh 72 2 dbnz opr,rel dbnza rel dbnzx rel dbnz opr, x ,rel dbnz x ,rel dbnz opr, sp ,rel decrement and branch if not zero a (a) ? 1 or m (m) ? 1 or x (x) ? 1 pc (pc) + 3 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 3 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 4 + rel ? (result) 0 ?????? dir inh inh ix1 ix sp1 3b 4b 5b 6b 7b 9e6b dd rr rr rr ff rr rr ff rr 5 3 3 5 4 6 dec opr deca decx dec opr ,x dec ,x dec opr ,sp decrement m (m) ? 1 a (a) ? 1 x (x) ? 1 m (m) ? 1 m (m) ? 1 m (m) ? 1 ?? ? dir inh inh ix1 ix sp1 3a 4a 5a 6a 7a 9e6a dd ff ff 4 1 1 4 3 5 div divide a (h:a)/(x) h remainder ???? inh 52 7 eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x eor opr ,sp eor opr ,sp exclusive or m with a a (a m) 0?? ? imm dir ext ix2 ix1 ix sp1 sp2 a8 b8 c8 d8 e8 f8 9ee8 9ed8 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 inc opr inca incx inc opr ,x inc ,x inc opr ,sp increment m (m) + 1 a (a) + 1 x (x) + 1 m (m) + 1 m (m) + 1 m (m) + 1 ?? ? dir inh inh ix1 ix sp1 3c 4c 5c 6c 7c 9e6c dd ff ff 4 1 1 4 3 5 table 6-1. instruction set summary (sheet 3 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc
instruction set summary mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 79 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x jump pc jump address ?????? dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc (pc) + n ( n = 1, 2, or 3) push (pcl); sp (sp) ? 1 push (pch); sp (sp) ? 1 pc unconditional address ?????? dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 4 5 6 5 4 lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x lda opr ,sp lda opr ,sp load a from m a (m) 0?? ? imm dir ext ix2 ix1 ix sp1 sp2 a6 b6 c6 d6 e6 f6 9ee6 9ed6 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ldhx # opr ldhx opr load h:x from m h:x ( m:m + 1 ) 0?? ? imm dir 45 55 ii jj dd 3 4 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x ldx opr ,sp ldx opr ,sp load x from m x (m) 0?? ? imm dir ext ix2 ix1 ix sp1 sp2 ae be ce de ee fe 9eee 9ede ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 lsl opr lsla lslx lsl opr ,x lsl ,x lsl opr ,sp logical shift left (same as asl) ?? dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 lsr opr lsra lsr x lsr opr ,x lsr ,x lsr opr ,sp logical shift right ??0 dir inh inh ix1 ix sp1 34 44 54 64 74 9e64 dd ff ff 4 1 1 4 3 5 mov opr,opr mov opr, x+ mov # opr,opr mov x+ ,opr move (m) destination (m) source h:x (h:x) + 1 (ix+d, dix+) 0?? ? dd dix+ imd ix+d 4e 5e 6e 7e dd dd dd ii dd dd 5 4 4 4 mul unsigned multiply x:a (x) (a) ?0???0inh 42 5 neg opr nega negx neg opr ,x neg ,x neg opr ,sp negate (two?s complement) m ?(m) = $00 ? (m) a ?(a) = $00 ? (a) x ?(x) = $00 ? (x) m ?(m) = $00 ? (m) m ?(m) = $00 ? (m) ?? dir inh inh ix1 ix sp1 30 40 50 60 70 9e60 dd ff ff 4 1 1 4 3 5 nop no operation none ??????inh 9d 1 nsa nibble swap a a (a[3:0]:a[7:4]) ??????inh 62 3 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x ora opr ,sp ora opr ,sp inclusive or a and m a (a) | (m) 0 ? ? ? imm dir ext ix2 ix1 ix sp1 sp2 aa ba ca da ea fa 9eea 9eda ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 psha push a onto stack push (a); sp (sp) ? 1 ??????inh 87 2 pshh push h onto stack push (h); sp (sp) ? 1 ??????inh 8b 2 pshx push x onto stack push (x); sp (sp) ? 1 ??????inh 89 2 table 6-1. instruction set summary (sheet 4 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 0 b0 b7 c 0
central processor unit (cpu) mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 80 freescale semiconductor pula pull a from stack sp (sp + 1); pull ( a ) ??????inh 86 2 pulh pull h from stack sp (sp + 1); pull ( h ) ??????inh 8a 2 pulx pull x from stack sp (sp + 1); pull ( x ) ??????inh 88 2 rol opr rola rolx rol opr ,x rol ,x rol opr ,sp rotate left through carry ?? dir inh inh ix1 ix sp1 39 49 59 69 79 9e69 dd ff ff 4 1 1 4 3 5 ror opr rora rorx ror opr ,x ror ,x ror opr ,sp rotate right through carry ?? dir inh inh ix1 ix sp1 36 46 56 66 76 9e66 dd ff ff 4 1 1 4 3 5 rsp reset stack pointer sp $ff ??????inh 9c 1 rti return from interrupt sp (sp) + 1; pull (ccr) sp (sp) + 1; pull (a) sp (sp) + 1; pull (x) sp (sp) + 1; pull (pch) sp (sp) + 1; pull (pcl) inh 80 7 rts return from subroutine sp sp + 1 ; pull ( pch) sp sp + 1; pull (pcl) ??????inh 81 4 sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x sbc opr ,sp sbc opr ,sp subtract with carry a (a) ? (m) ? (c) ?? imm dir ext ix2 ix1 ix sp1 sp2 a2 b2 c2 d2 e2 f2 9ee2 9ed2 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 sec set carry bit c 1 ?????1inh 99 1 sei set interrupt mask i 1 ??1???inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x sta opr ,sp sta opr ,sp store a in m m (a) 0?? ? dir ext ix2 ix1 ix sp1 sp2 b7 c7 d7 e7 f7 9ee7 9ed7 dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sthx opr store h:x in m (m:m + 1) (h:x) 0 ? ? ? dir 35 dd 4 stop enable interrupts, stop processing, refer to mcu documentation i 0; stop processing ??0???inh 8e 1 stx opr stx opr stx opr ,x stx opr ,x stx ,x stx opr ,sp stx opr ,sp store x in m m (x) 0?? ? dir ext ix2 ix1 ix sp1 sp2 bf cf df ef ff 9eef 9edf dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x sub opr ,sp sub opr ,sp subtract a (a) ? (m) ?? imm dir ext ix2 ix1 ix sp1 sp2 a0 b0 c0 d0 e0 f0 9ee0 9ed0 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 table 6-1. instruction set summary (sheet 5 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 b0 b7 c
opcode map mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 81 6.8 opcode map see table 6-2 . swi software interrupt pc (pc) + 1; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1; push (x) sp (sp) ? 1; push (a) sp (sp) ? 1; push (ccr) sp (sp) ? 1; i 1 pch interrupt vector high byte pcl interrupt vector low byte ??1???inh 83 9 tap transfer a to ccr ccr (a) inh 84 2 tax transfer a to x x (a) ??????inh 97 1 tpa transfer ccr to a a (ccr) ??????inh 85 1 tst opr tsta tstx tst opr ,x tst ,x tst opr ,sp test for negative or zero (a) ? $00 or (x) ? $00 or (m) ? $00 0 ? ? ? dir inh inh ix1 ix sp1 3d 4d 5d 6d 7d 9e6d dd ff ff 3 1 1 3 2 4 tsx transfer sp to h:x h:x (sp) + 1 ??????inh 95 2 txa transfer x to a a (x) ??????inh 9f 1 txs transfer h:x to sp (sp) (h:x) ? 1 ??????inh 94 2 wait enable interrupts; wait for interrupt i bit 0; inhibit cpu clocking until interrupted ??0???inh 8f 1 a accumulator n any bit c carry/borrow bit opr operand (one or two bytes) ccr condition code register pc program counter dd direct address of operand pch program counter high byte dd rr direct address of operand and relative offset of branch instruction pcl program counter low byte dd direct to direct addressing mode rel relative addressing mode dir direct addressing mode rel relative program counter offset byte dix+ direct to indexed with pos t increment addressing mode rr relati ve program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit offs et addressing sp1 stack pointer , 8-bit offset addressing mode ext extended addressing mode sp2 stack pointer 16-bit offset addressing mode ff offset byte in indexed, 8-bit offset addressing sp stack pointer h half-carry bit u undefined h index register high byte v overflow bit hh ll high and low bytes of operand address in extended addressing x index register low byte i interrupt mask z zero bit ii immediate operand byte & logical and imd immediate source to direct des tination addressing mode | logical or imm immediate addressing mode logical exclusive or inh inherent addressing mode ( ) contents of ix indexed, no offset addressing mode ?( ) negation (two?s complement) ix+ indexed, no offset, post increment addressing mode # immediate value ix+d indexed with post increment to direct addressing mode ? sign extend ix1 indexed, 8-bit offset addressing mode loaded with ix1+ indexed, 8-bit offset, pos t increment addressing mode ? if ix2 indexed, 16-bit offset addressing mode : concatenated with m memory location set or cleared n negative bit ? not affected table 6-1. instruction set summary (sheet 6 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc
mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 82 freescale semiconductor central processor unit (cpu) table 6-2. opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 sp1 ix inh inh imm dir ext ix2 sp2 ix1 sp1 ix 0 1 2 3 4 5 6 9e6 7 8 9 a b c d 9ed e 9ee f 0 5 brset0 3dir 4 bset0 2dir 3 bra 2rel 4 neg 2dir 1 nega 1inh 1 negx 1inh 4 neg 2ix1 5 neg 3 sp1 3 neg 1ix 7 rti 1inh 3 bge 2rel 2 sub 2imm 3 sub 2dir 4 sub 3ext 4 sub 3ix2 5 sub 4 sp2 3 sub 2ix1 4 sub 3 sp1 2 sub 1ix 1 5 brclr0 3dir 4 bclr0 2dir 3 brn 2rel 5 cbeq 3dir 4 cbeqa 3imm 4 cbeqx 3imm 5 cbeq 3ix1+ 6 cbeq 4 sp1 4 cbeq 2ix+ 4 rts 1inh 3 blt 2rel 2 cmp 2imm 3 cmp 2dir 4 cmp 3ext 4 cmp 3ix2 5 cmp 4 sp2 3 cmp 2ix1 4 cmp 3 sp1 2 cmp 1ix 2 5 brset1 3dir 4 bset1 2dir 3 bhi 2rel 5 mul 1inh 7 div 1inh 3 nsa 1inh 2 daa 1inh 3 bgt 2rel 2 sbc 2imm 3 sbc 2dir 4 sbc 3ext 4 sbc 3ix2 5 sbc 4 sp2 3 sbc 2ix1 4 sbc 3 sp1 2 sbc 1ix 3 5 brclr1 3dir 4 bclr1 2dir 3 bls 2rel 4 com 2dir 1 coma 1inh 1 comx 1inh 4 com 2ix1 5 com 3 sp1 3 com 1ix 9 swi 1inh 3 ble 2rel 2 cpx 2imm 3 cpx 2dir 4 cpx 3ext 4 cpx 3ix2 5 cpx 4 sp2 3 cpx 2ix1 4 cpx 3 sp1 2 cpx 1ix 4 5 brset2 3dir 4 bset2 2dir 3 bcc 2rel 4 lsr 2dir 1 lsra 1inh 1 lsrx 1inh 4 lsr 2ix1 5 lsr 3 sp1 3 lsr 1ix 2 ta p 1inh 2 txs 1inh 2 and 2imm 3 and 2dir 4 and 3ext 4 and 3ix2 5 and 4 sp2 3 and 2ix1 4 and 3 sp1 2 and 1ix 5 5 brclr2 3dir 4 bclr2 2dir 3 bcs 2rel 4 sthx 2dir 3 ldhx 3imm 4 ldhx 2dir 3 cphx 3imm 4 cphx 2dir 1 tpa 1inh 2 tsx 1inh 2 bit 2imm 3 bit 2dir 4 bit 3ext 4 bit 3ix2 5 bit 4 sp2 3 bit 2ix1 4 bit 3 sp1 2 bit 1ix 6 5 brset3 3dir 4 bset3 2dir 3 bne 2rel 4 ror 2dir 1 rora 1inh 1 rorx 1inh 4 ror 2ix1 5 ror 3 sp1 3 ror 1ix 2 pula 1inh 2 lda 2imm 3 lda 2dir 4 lda 3ext 4 lda 3ix2 5 lda 4 sp2 3 lda 2ix1 4 lda 3 sp1 2 lda 1ix 7 5 brclr3 3dir 4 bclr3 2dir 3 beq 2rel 4 asr 2dir 1 asra 1inh 1 asrx 1inh 4 asr 2ix1 5 asr 3 sp1 3 asr 1ix 2 psha 1inh 1 ta x 1inh 2 ais 2imm 3 sta 2dir 4 sta 3ext 4 sta 3ix2 5 sta 4 sp2 3 sta 2ix1 4 sta 3 sp1 2 sta 1ix 8 5 brset4 3dir 4 bset4 2dir 3 bhcc 2rel 4 lsl 2dir 1 lsla 1inh 1 lslx 1inh 4 lsl 2ix1 5 lsl 3 sp1 3 lsl 1ix 2 pulx 1inh 1 clc 1inh 2 eor 2imm 3 eor 2dir 4 eor 3ext 4 eor 3ix2 5 eor 4 sp2 3 eor 2ix1 4 eor 3 sp1 2 eor 1ix 9 5 brclr4 3dir 4 bclr4 2dir 3 bhcs 2rel 4 rol 2dir 1 rola 1inh 1 rolx 1inh 4 rol 2ix1 5 rol 3 sp1 3 rol 1ix 2 pshx 1inh 1 sec 1inh 2 adc 2imm 3 adc 2dir 4 adc 3ext 4 adc 3ix2 5 adc 4 sp2 3 adc 2ix1 4 adc 3 sp1 2 adc 1ix a 5 brset5 3dir 4 bset5 2dir 3 bpl 2rel 4 dec 2dir 1 deca 1inh 1 decx 1inh 4 dec 2ix1 5 dec 3 sp1 3 dec 1ix 2 pulh 1inh 2 cli 1inh 2 ora 2imm 3 ora 2dir 4 ora 3ext 4 ora 3ix2 5 ora 4 sp2 3 ora 2ix1 4 ora 3 sp1 2 ora 1ix b 5 brclr5 3dir 4 bclr5 2dir 3 bmi 2rel 5 dbnz 3dir 3 dbnza 2inh 3 dbnzx 2inh 5 dbnz 3ix1 6 dbnz 4 sp1 4 dbnz 2ix 2 pshh 1inh 2 sei 1inh 2 add 2imm 3 add 2dir 4 add 3ext 4 add 3ix2 5 add 4 sp2 3 add 2ix1 4 add 3 sp1 2 add 1ix c 5 brset6 3dir 4 bset6 2dir 3 bmc 2rel 4 inc 2dir 1 inca 1inh 1 incx 1inh 4 inc 2ix1 5 inc 3 sp1 3 inc 1ix 1 clrh 1inh 1 rsp 1inh 2 jmp 2dir 3 jmp 3ext 4 jmp 3ix2 3 jmp 2ix1 2 jmp 1ix d 5 brclr6 3dir 4 bclr6 2dir 3 bms 2rel 3 tst 2dir 1 tsta 1inh 1 tstx 1inh 3 tst 2ix1 4 tst 3 sp1 2 tst 1ix 1 nop 1inh 4 bsr 2rel 4 jsr 2dir 5 jsr 3ext 6 jsr 3ix2 5 jsr 2ix1 4 jsr 1ix e 5 brset7 3dir 4 bset7 2dir 3 bil 2rel 5 mov 3dd 4 mov 2dix+ 4 mov 3imd 4 mov 2ix+d 1 stop 1inh * 2 ldx 2imm 3 ldx 2dir 4 ldx 3ext 4 ldx 3ix2 5 ldx 4 sp2 3 ldx 2ix1 4 ldx 3 sp1 2 ldx 1ix f 5 brclr7 3dir 4 bclr7 2dir 3 bih 2rel 3 clr 2dir 1 clra 1inh 1 clrx 1inh 3 clr 2ix1 4 clr 3 sp1 2 clr 1ix 1 wait 1inh 1 txa 1inh 2 aix 2imm 3 stx 2dir 4 stx 3ext 4 stx 3ix2 5 stx 4 sp2 3 stx 2ix1 4 stx 3 sp1 2 stx 1ix inh inherent rel relative sp1 stack pointer, 8-bit offset imm immediate ix indexed, no offset sp2 stack pointer, 16-bit offset dir direct ix1 indexed, 8-bit offset ix+ indexed, no offset with ext extended ix2 indexed, 16-bit offset post increment dd direct-direct imd immediate-direct ix1+ indexed, 1-byte offset with ix+d indexed-direct dix+ direct-indexed post increment * pre-byte for stack pointer indexed instructions 0 high byte of opcode in hexadecimal low byte of opcode in hexadecimal 0 5 brset0 3dir cycles opcode mnemonic number of bytes / addressing mode msb lsb msb lsb
mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 83 chapter 7 external interrupt (irq) 7.1 introduction the irq (external interrupt) module provides a maskable interrupt input. 7.2 features features of the irq module include: a dedicated external interrupt pin (irq ) irq interrupt control bits hysteresis buffer programmable edge-only or edge and level interrupt sensitivity automatic interrupt acknowledge internal pullup resistor 7.3 functional description a low level applied to the external inte rrupt pin can latch a cpu interrupt request. figure 7-1 shows the structure of the irq module. figure 7-1. irq module block diagram imask dq ck clr irq high interrupt to mode select logic request v dd mode voltage detect irqf to cpu for bil/bih instructions vector fetch decoder internal address bus reset v dd internal pullup device ack irq synchronizer
external interrupt (irq) mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 84 freescale semiconductor figure 7-2. block diagram highlighting irq block and pins interrupt signals on the irq pin are latched into the irq latch. the interrupt latch remains set until one of the following actions occurs: vector fetch ? a vector fetch automatically gener ates an interrupt acknowledge signal that clears the latch that caused the vector fetch. software clear ? software can clear the interrupt latch by writing a 1 to the ack bit in the interrupt status and control register (intscr). reset ? a reset automatically clears the interrupt latch. single breakpoint break module clock generator module system integration module programmable timebase module monitor module serial peripheral 2-channel timer interface module 2 dual voltage low-voltage inhibit module 8-bit keyboard arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers user rom user ram monitor rom user rom vector space single external interrupt module porta ddra ddrc portc ddrd portd ddre porte internal bus osc1 osc2 cgmxfc rst (3) irq (3) interface module interrupt module computer operating properly module pta7/kbd7 ? ptb7/ad7 ptb6/ad6 ptb5/ad5 ptb4/ad4 ptb3/ad3 ptb2/ad2 ptb1/ad1 ptb0/ad0 v ddad /v refh 8-bit analog-to-digital converter module ptc6 (1) ptc5 (1) ptc4 (1, 2) ptc3 (1, 2) ptc2 (1, 2) ptc1 (1, 2) ptc0 (1, 2) ptd7/t2ch1 (1) ptd6/t2ch0 (1) ptd5/t1ch1 (1) ptd4/t1ch0 (1) ptd3/spsck (1) ptd2/mosi (1) ptd1/miso (1) ptd0/ss (1) pte1/rxd pte0/txd v ssad /v refl 2-channel timer interface module 1 32-khz oscillator phase-locked loop serial communications interface module power-on reset module memory map module mask option register 1 module security module mask option register 2 module power v ss v dd v ssa v dda 1. ports are software configurable with pullup device if input port. 2. higher current drive port pins 3. pin contains integrated pullup device ddrb portb 64 bytes pta0/kbd0 (1) mc68hc08gp32a ? 32,256 bytes 512 bytes 307 bytes 36 bytes mc68hc08gp16a ? 15,872 bytes
irq pin mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 85 the external interrupt pin is falling-edge-triggered and is software-configurable to be either falling-edge or falling-edge and low-level-triggered. the mode bit in the intscr controls the triggering sensitivity of the irq pin. when set, the imask bit in the intscr masks all external interrupt requests. a latched interrupt request is not presented to the interrupt priori ty logic unless the imask bit is clear. note the interrupt mask (i) in the condi tion code register (ccr) masks all interrupt requests, including external interrupt requests. 7.4 irq pin a falling edge on the irq pin can latch an interrupt request into the irq latch. a vector fetch, software clear, or reset clears the irq latch. if the mode bit is set, the irq pin is both falling-edge-sensitive a nd low-level-sensitive. with mode set, both of the following actions must occur to clear irq: vector fetch or software clear ? a vector fetch generates an interrupt acknowledge signal to clear the latch. software may generate the interrupt acknowledge signal by writing a 1 to the ack bit in the interrupt status and control register (intscr). t he ack bit is useful in applications that poll the irq pin and require software to clear the irq latch. writing to the ack bit prior to leaving an interrupt service routine can also prevent spur ious interrupts due to noise. setting ack does not affect subsequent transitions on the irq pin. a falling edge that occurs after writing to the ack bit another interrupt request. if the ir q mask bit, imask, is clear, the cpu loads the program counter with the vector address at locations $fffa and $fffb. return of the irq pin to a high level ? as long as the irq pin is low, irq remains active. the vector fetch or software clear and the return of the irq pin to a high level may occur in any order. the interrupt request remains pending as long as the irq pin is low. a reset will clear the latch and the mode control bit, thereby clearing the interrupt even if the pin stays low. if the mode bit is clear, the irq pin is falling-edge-sensitive only. with mode clear, a vector fetch or software clear immediately clears the irq latch. the irqf bit in the intscr register can be used to check for pending interrupts. the irqf bit is not affected by the imask bit, which makes it usef ul in applications where polling is preferred. use the bih or bil instruction to read the logic level on the irq pin. note when using the level-sensitive interrupt trigger, avoid false interrupts by masking interrupt requests in the interrupt routine. addr.register name bit 7654321bit 0 $001d irq status and control register (intscr) see page 86. read:0000irqf0 imask mode write: ack reset:00000000 = unimplemented figure 7-3. irq i/o register summary
external interrupt (irq) mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 86 freescale semiconductor 7.5 irq module duri ng break interrupts the bcfe bit in the sim break flag control register (sbfcr) enables software to clear the latch during the break state. see chapter 19 development support. to allow software to clear the irq latch during a break interrupt, write a 1 to the bcfe bit. if the latch is cleared during the break state, it remains cleared when the mcu exits the break state. to protect cpu interrupt flags during the break state, wr ite a 0 to the bcfe bit. with bcfe at 0 (its default state), writing to the ack bit in the irq status and control register during the break state has no effect on the irq interrupt flag. 7.6 irq status and control register the irq status and control register (intscr) contro ls and monitors operation of the irq module. the intscr: shows the state of the irq flag clears the irq latch masks irq interrupt request controls triggering sensitivity of the irq interrupt pin irqf ? irq flag bit this read-only status bit is set when the irq interrupt is pending. 1 = irq interrupt pending 0 = irq interrupt not pending ack ? irq interrupt request acknowledge bit writing a 1 to this write-only bit clears the irq latch. ack always reads as 0. reset clears ack. imask ? irq interrupt mask bit writing a 1 to this read/write bit disables irq interrupt requests. reset clears imask. 1 = irq interrupt requests disabled 0 = irq interrupt requests enabled mode ? irq edge/level select bit this read/write bit controls the triggering sensitivity of the irq pin. reset clears mode. 1 = irq interrupt requests on falling edges and low levels 0 = irq interrupt requests on falling edges only address: $001d bit 7654321bit 0 read:0000irqf0 imask mode write: ack reset:00000000 = unimplemented figure 7-4. irq status and control register (intscr)
mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 87 chapter 8 keyboard interrupt (kbi) module 8.1 introduction the keyboard interrupt module (kbi) provides eight independently maskable external interrupts which are accessible via pta0?pta7. when a port pin is enabled for keyboard interrupt function, an internal pullup device is also enabled on the pin. 8.2 features features include: eight keyboard interrupt pins with separate keyboard interrupt enable bits and one keyboard interrupt mask hysteresis buffers programmable edge-only or edge- and level- interrupt sensitivity exit from low-power modes i/o (input/output) port bit(s) software configurable with pullup device(s) if configured as input port bit(s) 8.3 functional description writing to the kbie7?kbie0 bits in the keyboard interrupt enable register independently enables or disables each port a pin as a keyboard interrupt pi n. enabling a keyboard interrupt pin also enables its internal pullup device. a falling edge applied to an enabled keyboard interrupt pin latches a keyboard interrupt request. a keyboard interrupt is latched when one or more keyb oard pins goes low after all were high. the modek bit in the keyboard status and control register cont rols the triggering mode of the keyboard interrupt. if the keyboard interrupt is edge-sensitive only, a falling edge on a keyboard pin does not latch an interrupt request if another keyboard pin is already low. to prevent losing an interrupt request on one pin because another pin is still low, softwar e can disable the latter pin while it is low. if the keyboard interrupt is falling edge- and low-level sensitive, an interrupt request is present as long as any keyboard interrupt pin is low and the pin is keyboard interrupt enabled.
keyboard interrupt (kbi) module mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 88 freescale semiconductor figure 8-1. block diagram highlighting kbi block and pins single breakpoint break module clock generator module system integration module programmable timebase module monitor module serial peripheral 2-channel timer interface module 2 dual voltage low-voltage inhibit module 8-bit keyboard arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers user rom user ram monitor rom user rom vector space single external interrupt module porta ddra ddrc portc ddrd portd ddre porte internal bus osc1 osc2 cgmxfc rst (3) irq (3) interface module interrupt module computer operating properly module pta7/kbd7 ? ptb7/ad7 ptb6/ad6 ptb5/ad5 ptb4/ad4 ptb3/ad3 ptb2/ad2 ptb1/ad1 ptb0/ad0 v ddad /v refh 8-bit analog-to-digital converter module ptc6 (1) ptc5 (1) ptc4 (1, 2) ptc3 (1, 2) ptc2 (1, 2) ptc1 (1, 2) ptc0 (1, 2) ptd7/t2ch1 (1) ptd6/t2ch0 (1) ptd5/t1ch1 (1) ptd4/t1ch0 (1) ptd3/spsck (1) ptd2/mosi (1) ptd1/miso (1) ptd0/ss (1) pte1/rxd pte0/txd v ssad /v refl 2-channel timer interface module 1 32-khz oscillator phase-locked loop serial communications interface module power-on reset module memory map module mask option register 1 module security module mask option register 2 module power v ss v dd v ssa v dda 1. ports are software configurable with pullup device if input port. 2. higher current drive port pins 3. pin contains int egrated pullup device ddrb portb 64 bytes pta0/kbd0 (1) mc68hc08gp32a ? 32,256 bytes 512 bytes 307 bytes 36 bytes mc68hc08gp16a ? 15,872 bytes
mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 89 functional description figure 8-2. keyboard module block diagram addr.register name bit 7654321bit 0 $001a keyboard status and control register (intkbscr) see page 92. read:0000keyf0 imaskk modek write: ackk reset:00000000 $001b keyboard interrupt enable register (intkbier) see page 92. read: kbie7 kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 = unimplemented figure 8-3. i/o register summary kb0ie kb7ie . . . keyboard interrupt dq ck clr v dd modek imaskk request vector fetch decoder ackk internal bus reset to pullup enable kbd7 kbd0 to pullup enable synchronizer keyf
keyboard interrupt (kbi) module mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 90 freescale semiconductor if the modek bit is set, the keyboard interrupt pins are both falling edge- and low-level sensitive, and both of the following actions must occur to clear a keyboard interrupt request: vector fetch or software clear ? a vector fetch generates an interrupt acknowledge signal to clear the interrupt request. software may generate the inte rrupt acknowledge signal by writing a 1 to the ackk bit in the keyboard status and control regi ster (intkbscr). the ackk bit is useful in applications that poll the keyboard interrupt pins and require software to clear the keyboard interrupt request. writing to the ackk bit prior to leaving an interrupt service routine can also prevent spurious interrupts due to noise. setting ackk does not affect subsequent transitions on the keyboard interrupt pins. a falling edge that oc curs after writing to the ackk bit latches another interrupt request. if the keyboard interrupt mask bit, imaskk, is clear, the cpu loads the program counter with the vector address at locations $ffe0 and $ffe1. return of all enabled keyboard interrupt pins to high level? as long as any enabled keyboard interrupt pin is low, the keyboard interrupt remains set. the vector fetch or software clear and the return of all enabled keyboard interrupt pins to a high level may occur in any order. if the modek bit is clear, the keyboard interrupt pin is falling-edge-sensitive only. with modek clear, a vector fetch or software clear immediately clears the keyboard interrupt request. reset clears the keyboard interrupt request and the mo dek bit, clearing the interrupt request even if a keyboard interrupt pin stays low. the keyboard flag bit (keyf) in the keyboard status and control register can be used to see if a pending interrupt exists. the keyf bit is not affected by t he keyboard interrupt mask bit (imaskk) which makes it useful in applications where polling is preferred. to determine the logic level on a keyboard interrupt pin, use the data direction register to configure the pin as an input and read the data register. note setting a keyboard interrupt enable bi t (kbiex) forces the corresponding keyboard interrupt pin to be an input, overriding the data direction register. however, the data direction register bit must be a 0 for software to read the pin. 8.4 keyboard initialization when a keyboard interrupt pin is enabled, it takes time for the internal pullup to reach a 1. therefore, a false interrupt can occur as soon as the pin is enabled. to prevent a false interrupt on keyboard initialization: 1. mask keyboard interrupts by setting the imaskk bit in the keyboard status and control register. 2. enable the kbi pins by setting the appropriate kbiex bits in the keyboard interrupt enable register. 3. write to the ackk bit in the keyboard status and control register to clear any false interrupts. 4. clear the imaskk bit. an interrupt signal on an edge-triggered pin can be acknowledged immediately a fter enabling the pin. an interrupt signal on an edge- and level-triggered interrupt pin must be acknowledged after a delay that depends on the external load.
low-power modes mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 91 another way to avoid a false interrupt: 1. configure the keyboard pins as outputs by setti ng the appropriate ddra bits in data direction register a. 2. write 1s to the appropriate port a data register bits. 3. enable the kbi pins by setting the appropriate kbiex bits in the keyboard interrupt enable register. 8.5 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 8.5.1 wait mode the keyboard module remains active in wait mode. clearing the imaskk bit in the keyboard status and control register enables keyboard interrupt requests to bring the mcu out of wait mode. 8.5.2 stop mode the keyboard module remain s active in stop mode. clearing the imaskk bit in the keyboard status and control register enables keyboard interrupt requests to bring the mcu out of stop mode. 8.6 keyboard module during break interrupts the system integration module (sim) controls whet her the keyboard interrupt latch can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bits during the break state. to allow software to clear the keyboard interrupt latch during a break interrupt, write a 1 to the bcfe bit. if a latch is cleared during the break state, it remains cleared when the mcu exits the break state. to protect the latch during the break state, write a 0 to the bcfe bit. with bcfe at 0 (its default state), writing to the keyboard acknowledge bit (ackk) in t he keyboard status and control register during the break state has no effect. see 8.7.1 keyboard status and control register. 8.7 i/o registers these registers control and monitor operation of the keyboard module: keyboard status and control register (intkbscr) keyboard interrupt enable register (intkbier) 8.7.1 keyboard status and contro l register the keyboard status and control register: flags keyboard interrupt requests acknowledges keyboard interrupt requests masks keyboard interrupt requests controls keyboard interrupt triggering sensitivity
keyboard interrupt (kbi) module mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 92 freescale semiconductor bits 7?4 ? not used these read-only bits always read as 0s. keyf ? keyboard flag bit this read-only bit is set when a keyboard inte rrupt is pending. reset clears the keyf bit. 1 = keyboard interrupt pending 0 = no keyboard interrupt pending ackk ? keyboard acknowledge bit writing a 1 to this write-only bit clears the keyboard interrupt request. ackk always reads as 0. reset clears ackk. imaskk ? keyboard interrupt mask bit writing a 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating interrupt requests. reset clears the imaskk bit. 1 = keyboard interrupt requests masked 0 = keyboard interrupt requests not masked modek ? keyboard triggering sensitivity bit this read/write bit controls the triggering sensitivity of the keyboard interrupt pins. reset clears modek. 1 = keyboard interrupt requests on falling edges and low levels 0 = keyboard interrupt requests on falling edges only 8.7.2 keyboard inte rrupt enable register the keyboard interrupt enable register enables or disables each port a pin to operate as a keyboard interrupt pin. kbie7?kbie0 ? keyboard interrupt enable bits each of these read/write bits enables the corre sponding keyboard interrupt pin to latch interrupt requests. reset clears the keyboard interrupt enable register. 1 = ptax pin enabled as keyboard interrupt pin 0 = ptax pin not enabled as keyboard interrupt pin address: $001a bit 7654321bit 0 read:0000keyf0 imaskk modek write: ackk reset:00000000 = unimplemented figure 8-4. keyboard status and control register (intkbscr) address: $001b bit 7654321bit 0 read: kbie7 kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 figure 8-5. keyboard interrupt enable register (intkbier)
mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 93 chapter 9 low-power modes 9.1 introduction the mcu may enter two low-power modes: wait mode and stop mode. they are common to all hc08 mcus and are entered through instruction execution. this section describes how each module acts in the low-power modes. 9.1.1 wait mode the wait instruction puts the mcu in a low-power standby mode in which the cpu clock is disabled but the bus clock continues to run. power consumpti on can be further reduced by disabling the lvi module and/or the timebase module through bits in the mask option (mor) register. see chapter 11 mask option registers (mor2 and mor1) . 9.1.2 stop mode stop mode is entered when a stop instruction is ex ecuted. the cpu clock is disabled and the bus clock is disabled if the oscstopenb bit in the mor register is 0. see chapter 11 mask option registers (mor2 and mor1) . 9.2 analog-to-digital converter (adc) 9.2.1 wait mode the adc continues normal operation du ring wait mode. any enabled cpu interrupt request from the adc can bring the mcu out of wait mode. if the adc is not required to bring the mcu out of wait mode, power down the adc by setting ad ch4?adch0 bits in the adc status and control register before executing the wait instruction. 9.2.2 stop mode the adc module is inactive after the execution of a stop instruction. any pending conversion is aborted. adc conversions resume when the mcu exits stop mode after an external interrupt. allow one conversion cycle to stabi lize the analog circuitry.
low-power modes mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 94 freescale semiconductor 9.3 break module (brk) 9.3.1 wait mode if enabled, the break module is active in wait mode. in the break routine, the user can subtract one from the return address on the stack if the sbsw bit in the break status register is set. 9.3.2 stop mode the break module is inactive in stop mode. the stop instruction does not affect break module register states. 9.4 central processor unit (cpu) 9.4.1 wait mode the wait instruction: clears the interrupt mask (i bit) in the condition code register, enabling interrupts. after exit from wait mode by interrupt, the i bit remains cl ear. after exit by reset, the i bit is set. disables the cpu clock 9.4.2 stop mode the stop instruction: clears the interrupt mask (i bit) in the conditi on code register, enabling external interrupts. after exit from stop mode by external interrupt, the i bit remains clear. after exit by reset, the i bit is set. disables the cpu clock after exiting stop mode, the cpu clock begins ru nning after the oscillator stabilization delay. 9.5 clock generator module (cgm) 9.5.1 wait mode the cgm remains active in wait mode. before entering wait mode, software can disengage and turn off the pll by clearing the bcs and pllon bits in the pll control register (pctl). less power-sensitive applications can disengage the pll without turning it off. applications that require the pll to wake the mcu from wait mode also can deselect the pll output without turning off the pll. 9.5.2 stop mode if the oscstopenb bit in the mor register is cleared (default), then the stop instruction disables the cgm (oscillator and phase-locked loop) and hold s low all cgm outputs (cgmxclk, cgmout, and cgmint). if the oscstopenb bit in the mor register is set, t hen the phase locked loop is shut off but the oscillator will continue to operate in stop mode.
computer operating properly module (cop) mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 95 9.6 computer operating properly module (cop) 9.6.1 wait mode the cop remains active during wait mode. if cop is enabled, a reset will occur at cop timeout. 9.6.2 stop mode stop mode turns off the cgmxclk input to the cop and clears the sim counter. service the cop immediately before entering or after exiting stop mode to ensure a full cop timeout period after entering or exiting stop mode. the stop bit in the mor register enables the stop instruction. to prevent inadvertently turning off the cop with a stop instruction, disable the stop instruction by clearing the stop bit. 9.7 external inte rrupt module (irq) 9.7.1 wait mode the irq module remains active in wait mode. clea ring the imask bit in the irq status and control register enables irq cpu interrupt requests to bring the mcu out of wait mode. 9.7.2 stop mode the irq module remains active in stop mode. clearing the imask bit in the irq status and control register enables irq cpu interrupt requests to bring the mcu out of stop mode. 9.8 keyboard interrupt module (kbi) 9.8.1 wait mode the keyboard module remains active in wait mode. clearing the imaskk bit in the keyboard status and control register enables keyboard interrupt requests to bring the mcu out of wait mode. 9.8.2 stop mode the keyboard module remain s active in stop mode. clearing the imaskk bit in the keyboard status and control register enables keyboard interrupt requests to bring the mcu out of stop mode. 9.9 low-voltage inhibit module (lvi) 9.9.1 wait mode if enabled, the lvi module remains active in wait m ode. if enabled to generate resets, the lvi module can generate a reset and bring the mcu out of wait mode. 9.9.2 stop mode if enabled, the lvi module remains active in st op mode. if enabled to generate resets, the lvi module can generate a reset and bring the mcu out of stop mode.
low-power modes mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 96 freescale semiconductor 9.10 serial communications interface module (sci) 9.10.1 wait mode the sci module remains active in wait mode. an y enabled cpu interrupt request from the sci module can bring the mcu out of wait mode. if sci module functions are not required during wait mode, reduce power consumption by disabling the module before executing the wait instruction. 9.10.2 stop mode the sci module is inactive in stop mode. the stop in struction does not affect sci register states. sci module operation resumes after the mcu exits stop mode. because the internal clock is inactive during st op mode, entering stop mode during an sci transmission or reception results in invalid data. 9.11 serial peripheral interface module (spi) 9.11.1 wait mode the spi module remains active in wait mode. an y enabled cpu interrupt request from the spi module can bring the mcu out of wait mode. if spi module functions are not required during wait mode, reduce power consumption by disabling the spi module before executing the wait instruction. 9.11.2 stop mode the spi module is inactive in stop mode. the stop instruction does not affect spi register states. spi operation resumes after an external interrupt. if stop mode is exited by reset, any transfer in progress is aborted, and the spi is reset. 9.12 timer interface mo dule (tim1 and tim2) 9.12.1 wait mode the tim remains active in wait mode. any enabled cp u interrupt request from the tim can bring the mcu out of wait mode. if tim functions are not required during wait mode, r educe power consumption by stopping the tim before executing the wait instruction. 9.12.2 stop mode the tim is inactive in stop mode. the stop instruction does not affect register states or the state of the tim counter. tim operation resumes when the mcu exits stop mode after an external interrupt.
timebase module (tbm) mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 97 9.13 timebase module (tbm) 9.13.1 wait mode the timebase module remains active after execution of the wait instruction. in wait mode, the timebase register is not accessible by the cpu. if the timebase functions are not required during wa it mode, reduce the power consumption by stopping the timebase before enabling the wait instruction. 9.13.2 stop mode the timebase module may remain active after execution of the stop instruction if the oscillator has been enabled to operate during stop mode through the oscstopenb bit in the mor register. the timebase module can be used in this mode to gener ate a periodic wakeup from stop mode. if the oscillator has not been enabled to operate in stop mode, the timebase module will not be active during stop mode. in stop mode, the timebase r egister is not accessible by the cpu. if the timebase functions are not required during st op mode, reduce the power consumption by stopping the timebase before enabling the stop instruction. 9.14 exiting wait mode these events restart the cpu clock and load the program counter with the reset vector or with an interrupt vector: external reset ? a low on the rst pin resets the mcu and loads the program counter with the contents of locations $fffe and $ffff. external interrupt ? a high-to-low trans ition on the external interrupt pin (irq pin) loads the program counter with the contents of locations: $fffa and $fffb; irq pin. break interrupt ? in emulation mode, a break inte rrupt loads the program counter with the contents of $fffc and $fffd. computer operating properly module (cop) reset ? a timeout of the cop counter resets the mcu and loads the program counter with the contents of $fffe and $ffff. low-voltage inhibit module (lvi) reset ? a power supply voltage below the v tripf voltage resets the mcu and loads the program counter with the contents of locations $fffe and $ffff. clock generator module (cgm) interrupt ? a cpu interrupt request from the phase-locked loop (pll) loads the program counter with the contents of $fff8 and $fff9. keyboard module (kbi) interrupt ? a cpu inte rrupt request from the kbi module loads the program counter with the contents of $ffe0 and $ffe1. timer 1 interface module (tim1) interrupt ? a cpu interrupt request from the tim1 loads the program counter with the contents of: ? $fff2 and $fff3; tim1 overflow ? $fff4 and $fff5; tim1 channel 1 ? $fff6 and $fff7; tim1 channel 0 timer 2 interface module (tim2) interrupt ? a cpu interrupt request from the tim2 loads the program counter with the contents of: ? $ffec and $ffed; tim2 overflow ? $ffee and $ffef; tim2 channel 1 ? $fff0 and $fff1; tim2 channel 0
low-power modes mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 98 freescale semiconductor serial peripheral interface module (spi) interrupt ? a cpu interrupt request from the spi loads the program counter with the contents of: ? $ffe8 and $ffe9; spi transmitter ? $ffea and $ffeb; spi receiver serial communications interface module (sci) in terrupt ? a cpu interrupt request from the sci loads the program counter with the contents of: ? $ffe2 and $ffe3; sci transmitter ? $ffe4 and $ffe5; sci receiver ? $ffe6 and $ffe7; sci receiver error analog-to-digital converter module (adc) interrupt ? a cpu interrupt request from the adc loads the program counter with the contents of: $ffde and $ffdf; adc conversion complete. timebase module (tbm) interrupt ? a cpu interru pt request from the tbm loads the program counter with the contents of: $ffdc and $ffdd; tbm interrupt. 9.15 exiting stop mode these events restart the system clocks and load the program counter with the reset vector or with an interrupt vector: external reset ? a low on the rst pin resets the mcu and loads the program counter with the contents of locations $fffe and $ffff. external interrupt ? a high-to-low transition on an external interrupt pin loads the program counter with the contents of locations: ? $fffa and $fffb; irq pin ? $ffe0 and $ffe1; keyboard interrupt pins low-voltage inhibit (lvi) reset ? a power supply voltage below the v tripf voltage resets the mcu and loads the program counter with the contents of locations $fffe and $ffff. timebase module (tbm) interrupt ? a tbm interrupt loads the program counter with the contents of locations $ffdc and $ffdd when the timebase counter has rolled over. this allows the tbm to generate a periodic wakeup from stop mode. upon exit from stop mode, the system clocks begin running after an o scillator stabilization delay. a 12-bit stop recovery counter inhibits the system clocks fo r 4096 cgmxclk cycles after the reset or external interrupt. the short stop recovery bit, ssrec, in the mor register controls the oscillator stabilization delay during stop recovery. setting ssrec reduces stop recovery time from 4096 cgmxclk cycles to 32 cgmxclk cycles. note use the full stop recovery time (ssrec = 0) in applications that use an external crystal unless the oscstopenb bit is set.
mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 99 chapter 10 low-voltage inhibit (lvi) 10.1 introduction this section describes the low-voltage inhibit (lvi) module, which monitors the voltage on the v dd pin and can force a reset when the v dd voltage falls below the lvi trip falling voltage, v tripf . 10.2 features features of the lvi module include: programmable lvi reset selectable lvi trip voltage programmable stop mode operation 10.3 functional description figure 10-1 shows the structure of the lvi module. the lvi module contains a bandgap reference circuit and comparator. clearing the lvi power disable bit, lvipwrd, enables the lvi to monitor v dd voltage. clearing the lvi reset disable bit, lvirstd, enab les the lvi module to generate a reset when v dd falls below a voltage, v tripf . setting the lvi enable in stop mode bit, lvistop, enables the lvi to operate in stop mode. setting the lvi 5-v or 3-v trip point bi t, lvi5or3, enables the trip point voltage, v tripf , to be configured for 5-v operation. clearing the lvi5or3 bit enables the trip point voltage, v tripf , to be configured for 3-v operation. the actual trip points are shown in chapter 20 electrical specifications . lvistop, lvipwrd, lvi5or3, and lvirstd are in the mask option register. see 11.2 mask option registers for details of the lvi?s configuration bits. once an lvi reset occurs, the mcu remains in reset until v dd rises above a voltage, v tripr , which causes the mcu to exit reset. see 15.3.2.5 low-voltage inhibit (lvi) reset for details of the interaction between the sim and the lvi. the output of the comparator controls the state of the lviout flag in the lvi status register (lvisr). an lvi reset also drives the rst pin low to provide low-voltage protection to external peripheral devices. 10.3.1 polled lvi operation in applications that can operate at v dd levels below the v tripf level, software can monitor v dd by polling the lviout bit. in the mask option register, the lvipwrd bit must be 0 to enable the lvi module, and the lvirstd bit must be 1 to disable lvi resets. 10.3.2 forced reset operation in applications that require v dd to remain above the v tripf level, enabling lvi resets allows the lvi module to reset the mcu when v dd falls below the v tripf level. in the mask option register, the lvipwrd and lvirstd bits must be 0 to enable the lvi module and to enable lvi resets.
low-voltage inhibit (lvi) mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 100 freescale semiconductor figure 10-1. lvi module block diagram 10.3.3 voltage hyst eresis protection once the lvi has triggered (by having v dd fall below v tripf ), the lvi will maintain a reset condition until v dd rises above the rising trip point voltage, v tripr . this prevents a condition in which the mcu is continually entering and exiting reset if v dd is approximately equal to v tripf . v tripr is greater than v tripf by the hysteresis voltage, v hys . 10.3.4 lvi trip selection the lvi5or3 bit in the mask option register selects whether the lvi is configured for 5-v or 3-v protection. note the microcontroller is guaranteed to operate at a minimum supply voltage. the trip point (v tripf [5 v] or v tripf [3 v]) may be lower than this. (see chapter 20 electrical specifications for the actual trip point voltages.) addr.register name bit 7654321bit 0 $fe0c lvi status register (lvisr) see page 101. read:lviout0000000 write: reset:00000000 = unimplemented figure 10-2. lvi i/o register summary low v dd detector lvipwrd stop instruction lvistop lvi reset lviout v dd > lvi trip = 0 v dd lvi trip = 1 from mor from mor v dd from mor lvirstd lvi5or3 from mor
lvi status register mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 101 10.4 lvi status register the lvi status register (lvisr) indicates if the v dd voltage was detected below the v tripf level. lviout ? lvi output bit this read-only flag becomes set when the v dd voltage falls below the v tripf trip voltage. see table 10-1 . reset clears the lviout bit. 10.5 lvi interrupts the lvi module does not generate interrupt requests. 10.6 low-power modes the stop and wait instructions put the mcu in low power-consumption standby modes. 10.6.1 wait mode if enabled, the lvi module remains active in wait m ode. if enabled to generate resets, the lvi module can generate a reset and bring the mcu out of wait mode. 10.6.2 stop mode if enabled in stop mode (lvistop set), the lvi module remains active in stop mode. if enabled to generate resets, the lvi module can generate a reset and bring the mcu out of stop mode. address: $fe0c bit 7654321bit 0 read:lviout0000000 write: reset:00000000 = unimplemented figure 10-3. lvi status register (lvisr) table 10-1. lviout bit indication v dd lviout v dd > v tripr 0 v dd < v tripf 1 v tripf < v dd < v tripr previous value
low-voltage inhibit (lvi) mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 102 freescale semiconductor
mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 103 chapter 11 mask option registers (mor2 and mor1) 11.1 introduction the two mask option registers at $001e and $001f (see figure 11-1 and figure 11-2 ) are read-only registers. they are defined by mask options (hard-wi red connections) specified at the same time as the read-only memory (rom) code submission. 11.2 mask option registers tbmclksel ? timebase clock select bit tbmclksel enables an enable of the extra divide-by-128 prescaler in the timebase module. setting this bit enables the extra prescaler and clearing this bit disables it. refer to table 17-1. timebase divider selection for timebase divider selection details 1 = enables extra divide-by-128 prescaler in timebase module 0 = disables extra divide-by-128 prescaler in timebase module oscstopenb? oscillator stop mode enable bar bit oscstopenb enables the oscillator to continue operating during stop mode. setting the oscstopenb bit allows the oscillator to operate c ontinuously even during stop mode. this is useful for driving the timebase module to allow it to generate periodic wakeup while in stop mode. (see 9.5 clock generator module (cgm) subsection 9.5.2 stop mode .) 1 = oscillator enabled to operate during stop mode 0 = oscillator disabled during stop mode scibdsrc ? sci baud rate clock source bit scibdsrc controls the clock source used for the sc i. the setting of this bit affects the frequency at which the sci operates. 1 = internal data bus clock used as clock source for sci 0 = external oscillator used as clock source for sci address: $001e bit 765432 1bit 0 read:00000 tbmclk- sel oscs- topenb scibdsrc write: reset: mask defined = unimplemented figure 11-1. mask option register 2 (mor2)
mask option register s (mor2 and mor1) mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 104 freescale semiconductor coprs ? cop rate select bit coprs selects the cop timeout period. see chapter 5 computer operating properly (cop). 1 = cop timeout period = 2 13 ? 2 4 cgmxclk cycles 0 = cop timeout period = 2 18 ? 2 4 cgmxclk cycles lvistop ? lvi enable in stop mode bit when the lvipwrd bit is clear, setting the lvisto p bit enables the lvi to operate during stop mode. see 9.5.2 stop mode . 1 = lvi enabled during stop mode 0 = lvi disabled during stop mode lvirstd ? lvi reset disable bit lvirstd disables the reset si gnal from the lvi module. see chapter 10 low-voltage inhibit (lvi). 1 = lvi module resets disabled 0 = lvi module resets enabled lvipwrd ? lvi power disable bit lvipwrd disables the lvi module. see chapter 10 low-voltage inhibit (lvi). 1 = lvi module power disabled 0 = lvi module power enabled lvi5or3 ? lvi 5-v or 3-v operating mode bit lvi5or3 selects the voltage operating mode of the lvi module. see chapter 10 low-voltage inhibit (lvi) . the voltage mode selected for the lvi should match the operating v dd . see chapter 20 electrical specifications for the lvi?s voltage trip points for each of the modes. 1 = lvi operates in 5-v mode 0 = lvi operates in 3-v mode ssrec ? short stop recovery bit ssrec enables the cpu to exit stop mode with a delay of 32 cgmxclk cycles instead of a 4096-cgmxclk cycle delay. 1 = stop mode recovery after 32 cgmxclk cycles 0 = stop mode recovery after 4096 cgmxclkc cycles note exiting stop mode by pulling reset will result in the long stop recovery. the short stop recovery delay can be enabled when using a crystal and the oscstopenb bit is set. the short stop recovery delay can be enabled when an external oscillator is used, regardless of the oscstopenb setting. the short stop recovery delay must be disabled when the oscstopenb bit is clear and a crystal is used. address: $001f bit 7654321bit 0 read: coprs lvistop lvirstd lvipwrd lvi5or3 ssrec stop copd write: reset: mask defined figure 11-2. mask option register 1 (mor1)
mask option registers mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 105 stop ? stop instruction enable bit stop enables the stop instruction. 1 = stop instruction enabled 0 = stop instruction treated as illegal opcode copd ? cop disable bit copd disables the cop module. see chapter 5 computer operating properly (cop). 1 = cop module disabled 0 = cop module enabled
mask option register s (mor2 and mor1) mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 106 freescale semiconductor
mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 107 chapter 12 input/output (i/o) ports 12.1 introduction thirty-three (33) bidirectional input-output (i/o) pins fo rm five parallel ports. all i/o pins are programmable as inputs or outputs. all individual bits within port a, port c, and port d are software configurable with pullup devices if configured as input port bits. t he pullup devices are automatically and dynamically disabled when a port bit is switched to output mode. note connect any unused i/o pins to an appropriate logic level, either v dd or v ss . although the i/o ports do not require termination for proper operation, termination reduces excess current consumption and the possibility of electrostatic damage. addr. register name bit 7654321bit 0 $0000 port a data register (pta) see page 110. read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 port b data register (ptb) see page 112. read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset $0002 port c data register (ptc) see page 114. read: 0 ptc6 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 write: reset: unaffected by reset $0003 port d data register (ptd) see page 116. read: ptd7 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset: unaffected by reset $0004 data direction register a (ddra) see page 110. read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 $0005 data direction register b (ddrb) see page 113. read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 = unimplemented figure 12-1. i/o port register summary
input/output (i/o) ports mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 108 freescale semiconductor $0006 data direction register c (ddrc) see page 114. read: 0 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset:00000000 $0007 data direction register d (ddrd) see page 117. read: ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset:00000000 $0008 port e data register (pte) see page 119. read:000000 pte1 pte0 write: reset: unaffected by reset $000c data direction register e (ddre) see page 120. read:000000 ddre1 ddre0 write: reset:00000000 $000d port a input pullup enable register (ptapue) see page 112. read: ptapue7 ptapue6 ptapue5 ptapue4 ptapue3 ptapue2 ptapue1 ptapue0 write: reset:00000000 $000e port c input pullup enable register (ptcpue) see page 116. read: 0 ptcpue6 ptcpue5 ptcpue4 ptcpue3 ptcpue2 ptcpue1 ptcpue0 write: reset:00000000 $000f port d input pullup enable register (ptdpue) see page 119. read: ptdpue7 ptdpue6 ptdpue5 ptdpue4 ptdpue3 ptdpue2 ptdpue1 ptdpue0 write: reset:00000000 addr. register name bit 7654321bit 0 = unimplemented figure 12-1. i/o port register summary (continued)
introduction mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 109 table 12-1. port control register bits summary port bit ddr module control pin a 0 ddra0 kbd kbie0 pta0/kbd0 1 ddra1 kbie1 pta1/kbd1 2 ddra2 kbie2 pta2/kbd2 3 ddra3 kbie3 pta3/kbd3 4 ddra4 kbie4 pta4/kbd4 5 ddra5 kbie5 pta5/kbd5 6 ddra6 kbie6 pta6/kbd6 7 ddra7 kbie7 pta7/kbd7 b 0 ddrb0 adc adch4?adch0 ptb0/ad0 1 ddrb1 ptb1/ad1 2 ddrb2 ptb2/ad2 3 ddrb3 ptb3/ad3 4 ddrb4 ptb4/ad4 5 ddrb5 ptb5/ad5 6 ddrb6 ptb6/ad6 7 ddrb7 ptb7/ad7 c 0 ddrc0 ptc0 1 ddrc1 ptc1 2 ddrc2 ptc2 3 ddrc3 ptc3 4 ddrc4 ptc4 5 ddrc5 ptc5 6 ddrc6 ptc6 d 0 ddrd0 spi spe ptd0/ss 1 ddrd1 ptd1/miso 2 ddrd2 ptd2/mosi 3 ddrd3 ptd3/spsck 4 ddrd4 tim1 els0b:els0a ptd4/t1ch0 5 ddrd5 els1b:el s1a ptd5/t1ch1 6 ddrd6 tim2 els0b:els0a ptd6/t2ch0 7 ddrd7 els1b:el s1a ptd7/t2ch1 e 0 ddre0 sci ensci pte0/txd 1 ddre1 pte1/rxd
input/output (i/o) ports mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 110 freescale semiconductor 12.2 port a port a is an 8-bit special-function port that shares all eight of its pins with the keyboard interrupt (kbi) module. port a also has software configurable pullup devices if configured as an input port. 12.2.1 port a data register the port a data register (pta) contains a data latch for each of the eight port a pins. pta7?pta0 ? port a data bits these read/write bits are software programmable. data direction of each port a pin is under the control of the corresponding bit in data direction regi ster a. reset has no effect on port a data. kbd7?kbd0 ? keyboard inputs the keyboard interrupt enable bits, kbie7?kbie0, in the keyboard interrupt control register (intkbier) enable the port a pins as external interrupt pins. see chapter 8 keyboard interrupt (kbi) module. 12.2.2 data dir ection register a data direction register a (ddra) determines whether each port a pin is an input or an output. writing a 1 to a ddra bit enables the output buffer for the corresponding port a pin; a 0 disables the output buffer. ddra7?ddra0 ? data direction register a bits these read/write bits control port a data directio n. reset clears ddra7?ddra0, configuring all port a pins as inputs. 1 = corresponding port a pin configured as output 0 = corresponding port a pin configured as input note avoid glitches on port a pins by writin g to the port a data register before changing data direction regist er a bits from 0 to 1. address: $0000 bit 7654321bit 0 read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset alternate function: kbd7 kbd6 kbd5 kbd4 kbd3 kbd2 kbd1 kbd0 figure 12-2. port a data register (pta) address: $0004 bit 7654321bit 0 read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 figure 12-3. data direction register a (ddra)
port a mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 111 figure 12-4 shows the port a i/o logic. figure 12-4. port a i/o circuit when bit ddrax is a 1, reading address $0000 reads the ptax data latch. when bit ddrax is a 0, reading address $0000 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 12-2 summarizes the operation of the port a pins. table 12-2. port a pin functions ptapue bit ddra bit pta bit i/o pin mode accesses to ddra accesses to pta read/write read write 10 x (1) input, v dd (4) ddra7?ddra0 pin pta7?pta0 (3) 00x input, hi-z (2) ddra7?ddra0 pin pta7?pta0 (3) x 1 x output ddra7?ddra0 pta7?pta0 pta7?pta0 1. x = don?t care 2. hi-z = high impedance 3. writing affects data register , but does not affect input. 4. i/o pin pulled up to v dd by internal pullup device read ddra ($0004) write ddra ($0004) reset write pta ($0000) read pta ($0000) ptax ddrax ptax internal data bus v dd ptapuex internal pullup device
input/output (i/o) ports mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 112 freescale semiconductor 12.2.3 port a input pullup enable register the port a input pullup enable register (ptapue) cont ains a software configur able pullup device for each of the eight port a pins. each bit is individually conf igurable and requires that the data direction register, ddra, bit be configured as an input. ea ch pullup is automati cally and dynamically disabled when a port bit?s ddra is configured for output mode. ptapue7?ptapue0 ? port a input pullup enable bits these writable bits are software programmable to enable pullup devices on an input port bit. 1 = corresponding port a pin configured to have internal pullup 0 = corresponding port a pin has internal pullup disconnected 12.3 port b port b is an 8-bit special-function port that shares al l eight of its pins with the analog-to-digital converter (adc) module. 12.3.1 port b data register the port b data register (ptb) contains a data latch for each of the eight port pins. ptb7?ptb0 ? port b data bits these read/write bits are software-programmable. data direction of each port b pin is under the control of the corresponding bit in data direction regi ster b. reset has no effect on port b data. ad7?ad0 ? analog-to-digital input bits ad7?ad0 are pins used for the input channels to the analog-to-digital converter module. the channel select bits in the adc status and control register define which port b pin will be used as an adc input and overrides any control from the port i/o logic by forcing that pin as the input to the analog circuitry. note care must be taken when reading port b while applying analog voltages to ad7?ad0 pins. if the appropriate adc channel is not enabled, excessive current drain may occur if analog voltages are applied to the ptbx/adx pin, while ptb is read as a digital input. those ports not selected as analog input channels are considered digital i/o ports. address: $000d bit 7654321bit 0 read: ptapue7 ptapue6 ptapue5 ptapue4 ptapue3 ptapue2 ptapue1 ptapue0 write: reset:00000000 figure 12-5. port a input pullup enable register (ptapue) address: $0001 bit 7654321bit 0 read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset alternate function: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 figure 12-6. port b data register (ptb)
port b mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 113 12.3.2 data dir ection register b data direction register b (ddrb) determines whether eac h port b pin is an input or an output. writing a 1 to a ddrb bit enables the output buffer for the co rresponding port b pin; a 0 disables the output buffer. ddrb7?ddrb0 ? data direction register b bits these read/write bits control port b data directio n. reset clears ddrb7?ddrb0, configuring all port b pins as inputs. 1 = corresponding port b pin configured as output 0 = corresponding port b pin configured as input note avoid glitches on port b pins by writin g to the port b data register before changing data direction regist er b bits from 0 to 1. figure 12-8 shows the port b i/o logic. figure 12-8. port b i/o circuit when bit ddrbx is a 1, reading address $0001 reads the ptbx data latch. when bit ddrbx is a 0, reading address $0001 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 12-3 summarizes the operation of the port b pins. address: $0005 bit 7654321bit 0 read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 figure 12-7. data direction register b (ddrb) table 12-3. port b pin functions ddrb bit ptb bit i/o pin mode accesses to ddrb accesses to ptb read/write read write 0 x (1) input, hi-z (2) ddrb7?ddrb0 pin ptb7?ptb0 (3) 1 x output ddrb7?ddrb0 ptb7?ptb0 ptb7?ptb0 1. x = don?t care 2. hi-z = high impedance 3. writing affects data register , but does not affect input. read ddrb ($0005) write ddrb ($0005) reset write ptb ($0001) read ptb ($0001) ptbx ddrbx ptbx internal data bus
input/output (i/o) ports mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 114 freescale semiconductor 12.4 port c port c is a 7-bit, general-purpose bidirectional i/o port. port c also has software configurable pullup devices if configured as an input port. 12.4.1 port c data register the port c data register (ptc) contains a dat a latch for each of the seven port c pins. note bit 6 and bit 5 of ptc are not available in the 42-pin shrink dual in-line package. ptc6?ptc0 ? port c data bits these read/write bits are software-programmable. da ta direction of each port c pin is under the control of the corresponding bit in data direction register c. reset has no effect on port c data. 12.4.2 data dir ection register c data direction register c (ddrc) determines whether ea ch port c pin is an input or an output. writing a 1 to a ddrc bit enables the output buffer for the corresponding port c pin; a 0 disables the output buffer. ddrc6?ddrc0 ? data direction register c bits these read/write bits control po rt c data direction. reset clears ddrc6?ddrc0, configuring all port c pins as inputs. 1 = corresponding port c pin configured as output 0 = corresponding port c pin configured as input note avoid glitches on port c pins by writin g to the port c data register before changing data direction regist er c bits from 0 to 1. address: $0002 bit 7654321bit 0 read: 0 ptc6 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 write: reset: unaffected by reset = unimplemented figure 12-9. port c data register (ptc) address: $0006 bit 7654321bit 0 read: 0 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset:00000000 = unimplemented figure 12-10. data direction register c (ddrc)
port c mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 115 figure 12-11 shows the port c i/o logic. note for those devices packaged in a 42-pin shrink dual in-line package, ptc5 and ptc6 are connected to ground internally. ddrc5 and ddrc6 should be set to a 0 to configure ptc5 and ptc6 as inputs. figure 12-11. port c i/o circuit when bit ddrcx is a 1, reading address $0002 reads the ptcx data latch. when bit ddrcx is a 0, reading address $0002 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 12-4 summarizes the operation of the port c pins. table 12-4. port c pin functions ptcpue bit ddrc bit ptc bit i/o pin mode accesses to ddrc accesse to ptc read/write read write 10 x (1) input, v dd (4) ddrc6?ddrc0 pin ptc6?ptc0 (3) 00x input, hi-z (2) ddrc6?ddrc0 pin ptc6?ptc0 (3) x 1 x output ddrc6?ddrc0 ptc6?ptc0 ptc6?ptc0 1. x = don?t care 2. hi-z = high impedance 3. writing affects data register , but does not affect input. 4. i/o pin pulled up to v dd by internal pullup device. read ddrc ($0006) write ddrc ($0006) reset write ptc ($0002) read ptc ($0002) ptcx ddrcx ptcx internal data bus v dd ptcpuex internal pullup device
input/output (i/o) ports mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 116 freescale semiconductor 12.4.3 port c input pullup enable register the port c input pullup enable register (ptcpue) co ntains a software configur able pullup device for each of the seven port c pins. each bit is individually c onfigurable and requires that the data direction register, ddrc, bit be configured as an input. each pullup is automatically and dynamically disabled when a port bit?s ddrc is configured for output mode. ptcpue6?ptcpue0 ? port c input pullup enable bits these writable bits are software programmable to enable pullup devices on an input port bit. 1 = corresponding port c pin configured to have internal pullup 0 = corresponding port c pin internal pullup disconnected 12.5 port d port d is an 8-bit special-function port that shares four of its pins with the serial peripheral interface (spi) module and four of its pins with two timer interfac e (tim1 and tim2) modules. port d also has software configurable pullup devices if configured as an input port. 12.5.1 port d data register the port d data register (ptd) contains a data latch for each of the eight port d pins. ptd7?ptd0 ? port d data bits these read/write bits are software-programmable. da ta direction of each port d pin is under the control of the corresponding bit in data direction register d. reset has no effect on port d data. t2ch1 and t2ch0 ? timer 2 channel i/o bits the ptd7/t2ch1?ptd6/t2ch0 pins are the tim2 input capture/output compare pins. the edge/level select bits, elsxb:elsxa, dete rmine whether the ptd7/t2ch1?ptd 6/t2ch0 pins are timer channel i/o pins or general-purpose i/o pins. see chapter 18 timer interface modules (tim1 and tim2) . address: $000e bit 7654321bit 0 read: 0 ptcpue6 ptcpue5 ptcpue4 ptcpue3 ptcpue2 ptcpue1 ptcpue0 write: reset:00000000 = unimplemented figure 12-12. port c input pullup enable register (ptcpue) address: $0003 bit 7654321bit 0 read: ptd7 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset: unaffected by reset alternate function: t2ch1 t2ch0 t1ch1 t1ch0 spsck mosi miso ss figure 12-13. port d data register (ptd)
port d mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 117 t1ch1 and t1ch0 ? timer 1 channel i/o bits the ptd5/t1ch1?ptd4/t1ch0 pins are the tim1 input capture/output compare pins. the edge/level select bits, elsxb and elsxa, determine whether the ptd5/t1ch1?ptd4/t1ch0 pins are timer channel i/o pins or general-purpose i/o pins. see chapter 18 timer interface modules (tim1 and tim2) . spsck ? spi serial clock the ptd3/spsck pin is the serial clock input of the spi module. when the spe bit is clear, the ptd3/spsck pin is availabl e for general-purpose i/o. mosi ? master out/slave in the ptd2/mosi pin is the master out/slave in term inal of the spi module. when the spe bit is clear, the ptd2/mosi pin is available for general-purpose i/o. miso ? master in/slave out the ptd1/miso pin is the master in/slave out term inal of the spi module. when the spi enable bit, spe, is clear, the spi module is disabled, and the pt d1/miso pin is availabl e for general-purpose i/o. data direction register d (ddrd) does not affect th e data direction of port d pins that are being used by the spi module. however, the ddrd bits alwa ys determine whether reading port d returns the states of the latches or the states of the pins. see table 12-5 . ss ? slave select the ptd0/ss pin is the slave select input of the sp i module. when the spe bit is clear, or when the spi master bit, spmstr, is set, the ptd0/ss pin is available for gener al-purpose i/o. when the spi is enabled, the ddrd0 bit in data direction register d (ddrd) has no effect on the ptd0/ss pin. 12.5.2 data dir ection register d data direction register d (ddrd) determines whether ea ch port d pin is an input or an output. writing a 1 to a ddrd bit enables the output buffer for the corresponding port d pin; a 0 disables the output buffer. ddrd7?ddrd0 ? data direction register d bits these read/write bits control po rt d data direction. reset clears ddrd7?ddrd0, configuring all port d pins as inputs. 1 = corresponding port d pin configured as output 0 = corresponding port d pin configured as input note avoid glitches on port d pins by writin g to the port d data register before changing data direction regist er d bits from 0 to 1. address: $0007 bit 7654321bit 0 read: ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset:00000000 figure 12-14. data direction register d (ddrd)
input/output (i/o) ports mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 118 freescale semiconductor figure 12-15 shows the port d i/o logic. figure 12-15. port d i/o circuit when bit ddrdx is a 1, reading address $0003 reads the ptdx data latch. when bit ddrdx is a 0, reading address $0003 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 12-5 summarizes the operation of the port d pins. table 12-5. port d pin functions ptdpue bit ddrd bit ptd bit i/o pin mode accesses to ddrd accesse to ptd read/write read write 10 x (1) input, v dd (4) ddrd7?ddrd0 pin ptd7?ptd0 (3) 00x input, hi-z (2) ddrd7?ddrd0 pin ptd7?ptd0 (3) x 1 x output ddrd7?ddrd0 ptd7?ptd0 ptd7?ptd0 1. x = don?t care 2. hi-z = high impedance 3. writing affects data register , but does not affect input. 4. i/o pin pulled up to v dd by internal pullup device. read ddrd ($0007) write ddrd ($0007) reset write ptd ($0003) read ptd ($0003) ptdx ddrdx ptdx internal data bus v dd ptdpuex internal pullup device
port e mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 119 12.5.3 port d input pullup enable register the port d input pullup enable register (ptdpue) co ntains a software configur able pullup device for each of the eight port d pins. each bit is individually configurable and require s that the data direction register, ddrd, bit be configured as an input. each pullup is automatically and dynamically disabled when a port bit?s ddrd is configured for output mode. ptdpue7?ptdpue0 ? port d input pullup enable bits these writable bits are software programmable to enable pullup devices on an input port bit. 1 = corresponding port d pin configured to have internal pullup 0 = corresponding port d pin ha s internal pullup disconnected 12.6 port e port e is a 2-bit special-function por t that shares two of its pins with the serial communications interface (sci) module. 12.6.1 port e data register the port e data register contains a data latch for each of the two port e pins. pte1 and pte0 ? port e data bits pte1 and pte0 are read/write, software programmable bits. data direction of each port e pin is under the control of the corresponding bit in data direction register e. note data direction register e (ddre) does not affect the data direction of port e pins that are being used by the sci module. however, the ddre bits always determine whether reading port e returns the states of the latches or the states of the pins. see table 12-6 . address: $000f bit 7654321bit 0 read: ptdpue7 ptdpue6 ptdpue5 ptdpue4 ptdpue3 ptdpue2 ptdpue1 ptdpue0 write: reset:00000000 figure 12-16. port d input pullup enable register (ptdpue) address: $0008 bit 7654321bit 0 read:000000 pte1 pte0 write: reset: unaffected by reset alternate function: rxd txd = unimplemented figure 12-17. port e data register (pte)
input/output (i/o) ports mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 120 freescale semiconductor rxd ? sci receive data input the pte1/rxd pin is the receive data input for the sci module. when the enable sci bit, ensci, is clear, the sci module is disabled, and the pte1/rxd pin is available for general-purpose i/o. see chapter 14 serial communications interface (sci) module . txd ? sci transmit data output the pte0/txd pin is the transmit data output for the sci module. when the enable sci bit, ensci, is clear, the sci module is disabled, and the pte0/txd pin is available for general-purpose i/o. see chapter 14 serial communications interface (sci) module . 12.6.2 data dir ection register e data direction register e (ddre) determines whether eac h port e pin is an input or an output. writing a 1 to a ddre bit enables the output buffer for the co rresponding port e pin; a 0 disables the output buffer. ddre1 and ddre0 ? data direction register e bits these read/write bits control port e data directio n. reset clears ddre1 and ddre0, configuring all port e pins as inputs. 1 = corresponding port e pin configured as output 0 = corresponding port e pin configured as input note avoid glitches on port e pins by writin g to the port e data register before changing data direction regist er e bits from 0 to 1. figure 12-19 shows the port e i/o logic. figure 12-19. port e i/o circuit address: $000c bit 7654321bit 0 read:000000 ddre1 ddre0 write: reset:00000000 = unimplemented figure 12-18. data direction register e (ddre) read ddre ($000c) write ddre ($000c) reset write pte ($0008) read pte ($0008) ptex ddrex ptex internal data bus
port e mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 121 when bit ddrex is a 1, reading address $0008 reads the ptex data latch. when bit ddrex is a 0, reading address $0008 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 12-6 summarizes the operation of the port e pins. table 12-6. port e pin functions ddre bit pte bit i/o pin mode accesses to ddre accesses to pte read/write read write 0 x (1) input, hi-z (2) ddre1?ddre0 pin pte1?pte0 (3) 1 x output ddre1?ddre0 pte1?pte0 pte1?pte0 1. x = don?t care 2. hi-z = high impedance 3. writing affects data register , but does not affect input.
input/output (i/o) ports mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 122 freescale semiconductor
mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 123 chapter 13 resets and interrupts 13.1 introduction resets and interrupts are responses to exceptional event s during program execution. a reset re-initializes the mcu to its startup condition. an interrupt vectors the program counter to a service routine. 13.2 resets a reset immediately returns the mcu to a known star tup condition and begins program execution from a user-defined memory location. 13.2.1 effects a reset: immediately stops the operation of the instruction being executed initializes certain control and status bits loads the program counter with a user-defined reset vector address from locations $fffe and $ffff selects cgmxclk divided by four as the bus clock 13.2.2 external reset a low applied to the rst pin for a time, t rl , generates an external reset. an external reset sets the pin bit in the sim reset status register. 13.2.3 internal reset sources: power-on reset (por) computer operating properly (cop) low-power reset circuits illegal opcode illegal address all internal reset sources pull the rst pin low for 32 cgmxclk cycles to allow resetting of external devices. the mcu is held in reset for an additional 32 cgmxclk cycles after releasing the rst pin.
resets and interrupts mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 124 freescale semiconductor figure 13-1. internal reset timing 13.2.3.1 power-on reset a power-on reset (por) is an internal reset caused by a positive transition on the v dd pin. v dd at the por must below v por to reset the mcu. this distinguishes between a reset and a por. the por is not a brown-out detector, low-voltage detector, or glitch detector. a power-on reset: holds the clocks to the cpu and modules inactive for an oscill ator stabilization delay of 4096 cgmxclk cycles drives the rst pin low during the oscillator stabilization delay releases the rst pin 32 cgmxclk cycles after the oscillator stabilization delay releases the cpu to begin the reset vector se quence 64 cgmxclk cycles after the oscillator stabilization delay sets the por bit in the sim reset status regi ster and clears all other bits in the register figure 13-2. power-on reset recovery rst pin pulled low by mcu internal 32 cycles 32 cycles cgmxclk reset porrst (1) osc1 cgmxclk cgmout rst pin internal 4096 cycles 32 cycles 32 cycles 1. porrst is an internally generated power-on reset pulse. reset
resets mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 125 13.2.3.2 cop reset a cop reset is an internal reset caused by an over flow of the cop counter. a cop reset sets the cop bit in the system integration m odule (sim) reset status register. to clear the cop counter and prevent a cop reset, write any value to the cop control register at location $ffff. 13.2.3.3 low-voltage inhibit reset a low-voltage inhibit (lvi) reset is an internal reset caused by a drop in the power supply voltage to the v tripf voltage. an lvi reset: holds the clocks to the cpu and modules inactive for an oscill ator stabilization delay of 4096 cgmxclk cycles after the power supply voltage rises to the lvi tripr voltage drives the rst pin low for as long as v dd is below the v tripr voltage and during the oscillator stabilization delay releases the rst pin 32 cgmxclk cycles after the oscillator stabilization delay releases the cpu to begin the reset vector se quence 64 cgmxclk cycles after the oscillator stabilization delay sets the lvi bit in the sim reset status register 13.2.3.4 illegal opcode reset an illegal opcode reset is an internal reset caused by an opcode that is not in the instruction set. an illegal opcode reset sets the ilop bit in the sim reset status register. if the stop enable bit, stop, in the mask option regist er is 0, the stop instruction causes an illegal opcode reset. 13.2.3.5 illegal address reset an illegal address reset is an internal reset caused by opcode fetch from an unmapped address. an illegal address reset sets the ilad bit in the sim reset status register. a data fetch from an unmapped address does not generate a reset. 13.2.4 sim reset status register this read-only register contains flags to show rese t sources. all flag bits are automatically cleared following a read of the register. reset service can read the sim reset status register to clear the register after power-on reset and to determine the source of any subsequent reset.
resets and interrupts mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 126 freescale semiconductor the register is initialized on power-up as shown with the por bit set and all other bits cleared. during a por or any other internal reset, the rst pin is pulled low. after the pin is released, it will be sampled 32 cgmxclk cycles later. if the pin is not above a v ih at that time, then the pin bit in the srsr may be set in addition to whatever other bits are set. note only a read of the sim reset status register clears all reset flags. after multiple resets from different sources without reading the register, multiple flags remain set. por ? power-on reset flag 1 = power-on reset since last read of srsr 0 = read of srsr since last power-on reset pin ? external reset flag 1 = external reset via rst pin since last read of srsr 0 = por or read of srsr since last external reset cop ? computer operating properly reset bit 1 = last reset caused by timeout of cop counter 0 = por or read of srsr ilop ? illegal opcode reset bit 1 = last reset caused by an illegal opcode 0 = por or read of srsr ilad ? illegal address reset bit 1 = last reset caused by an opcode fetch from an illegal address 0 = por or read of srsr lvi ? low-voltage inhibit reset bit 1 = last reset caused by low-power supply voltage 0 = por or read of srsr address: $fe01 bit 7654321bit 0 read: por pin cop ilop ilad 0 lvi 0 write: por:10000000 = unimplemented r = reserved figure 13-3. sim reset status register (srsr)
interrupts mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 127 13.3 interrupts an interrupt temporarily changes the sequence of progr am execution to respond to a particular event. an interrupt does not stop the operation of the instruction being executed, but begins when the current instruction completes its operation. 13.3.1 effects an interrupt: saves the cpu registers on the stack. at the end of the interrupt, the rti instruction recovers the cpu registers from the stack so that normal processing can resume. sets the interrupt mask (i bit) to prevent additional interrupts. once an interrupt is latched, no other interrupt can take precedence, regardless of its priority. loads the program counter with a user-defined vector address figure 13-4. interrupt stacking order after every instruction, the cpu checks all pending interrupts if the i bit is not set. if more than one interrupt is pending when an instruction is done, the hi ghest priority interrupt is serviced first. in the example shown in figure 13-5 , if an interrupt is pending upon exit from the interrupt service routine, the pending interrupt is serviced before the lda instruction is executed. condition code register accumulator index register (low byte)* program counter (high byte) program counter (low byte) 1 2 3 4 5 5 4 3 2 1 stacking order *high byte of index register is not stacked. $00ff default address on reset unstacking order
resets and interrupts mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 128 freescale semiconductor figure 13-5 . interrupt recognition example the lda opcode is prefetched by both the int1 and int2 rti instructions. however, in the case of the int1 rti prefetch, this is a redundant operation. note to maintain compatibility with the m6805 family, the h register is not pushed on the stack during interrupt entry. if the interrupt service routine modifies the h register or uses th e indexed addressing mode, save the h register and then restore it prior to exiting the routine. 13.3.2 sources the sources in table 13-1 can generate cpu interrupt requests. 13.3.2.1 swi instruction the software interrupt instruction (swi) causes a non-maskable interrupt. note a software interrupt pushes pc onto the stack. an swi does not push pc ? 1, as a hardware interrupt does. 13.3.2.2 break interrupt the break module causes the cpu to execute an sw i instruction at a software-programmable break point. cli lda int1 pulh rti int2 background #$ff pshh int1 interrupt service routine pulh rti pshh int2 interrupt service routine routine
interrupts mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 129 figure 13-6. interrupt processing no no no yes no no yes no yes yes from reset break i bit set? irq interrupt cgm interrupt fetch next instruction unstack cpu registers stack cpu registers set i bit load pc with interrupt vector execute instruction yes yes i bit set? interrupt yes other interrupts no swi instruction rti instruction ? ? ? ? ? ?
resets and interrupts mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 130 freescale semiconductor 13.3.2.3 irq pin a falling edge on the irq pin latches an external interrupt request. 13.3.2.4 cgm the cgm can generate a cpu interrupt request every ti me the phase-locked loop circuit (pll) enters or leaves the locked state. when the lock bit changes state, the pll flag (pllf) is set. the pll interrupt enable bit (pllie) enables pllf cpu interrupt requests. lock is in the pll bandwidth control register. pllf is in the pll control register. table 13-1. interrupt sources source flag mask (1) 1. the i bit in the condition code register is a global mask for all interrupt sources except the swi instruction. int register flag priority (2) 2. 0 = highest priority vector address reset none none none 0 $fffe ? $ffff swi instruction none none none 0 $fffc ? $fffd irq pin irqf imask if1 1 $fffa ? $fffb cgm (pll) pllf pllie if2 2 $fff8?$fff9 tim1 channel 0 ch0f ch0ie if3 3 $fff6?$fff7 tim1 channel 1 ch1f ch1ie if4 4 $fff4?$fff5 tim1 overflow tof toie if5 5 $fff2?$fff3 tim2 channel 0 ch0f ch0ie if6 6 $fff0?$fff1 tim2 channel 1 ch1f ch1ie if7 7 $ffee?$ffef tim2 overflow tof toie if8 8 $ffec?$ffed spi receiver full sprf sprie if9 9 $ffea?$ffeb spi overflow ovrf errie spi mode fault modf errie spi transmitter empty spte sptie if10 10 $ffe8?$ffe9 sci receiver overrun or orie if11 11 $ffe6?$ffe7 sci noise flag nf neie sci framing error fe feie sci parity error pe peie sci receiver full scrf scrie if12 12 $ffe4?$ffe5 sci input idle idle ilie sci transmitter empty scte sctie if13 13 $ffe2?$ffe3 sci transmission complete tc tcie keyboard pin keyf imaskk if14 14 $ffe0?$ffe1 adc conversion complete coco aien if15 15 $ffde?$ffdf timebase tbif tbie if16 16 $ffdc?$ffdd
interrupts mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 131 13.3.2.5 tim1 tim1 cpu interrupt sources: tim1 overflow flag (tof) ? the tof bit is set when the tim1 counter reaches the modulo value programmed in the tim1 counter modulo registers. the tim1 overflow interrupt enable bit, toie, enables tim1 overflow cpu interrupt requests. to f and toie are in the tim1 status and control register. tim1 channel flags (ch1f?ch0f) ? the chxf bit is set when an input capture or output compare occurs on channel x. the channel x interrupt enable bit, chxie, enables channel x tim1 cpu interrupt requests. chxf and chxie are in the tim1 channel x status and control register. 13.3.2.6 tim2 tim2 cpu interrupt sources: tim2 overflow flag (tof) ? the tof bit is set when the tim2 counter reaches the modulo value programmed in the tim2 counter modulo registers. the tim2 overflow interrupt enable bit, toie, enables tim2 overflow cpu interrupt requests. to f and toie are in the tim2 status and control register. tim2 channel flags (ch1f?ch0f) ? the chxf bit is set when an input capture or output compare occurs on channel x. the channel x interrupt enable bit, chxie, enables channel x tim2 cpu interrupt requests. chxf and chxie are in the tim2 channel x status and control register. 13.3.2.7 spi spi cpu interrupt sources: spi receiver full bit (sprf) ? the sprf bit is set every time a byte transfers from the shift register to the receive data register. the spi receiver interrupt enable bit, sprie, enables sprf cpu interrupt requests. sprf is in the spi status and control register and sprie is in the spi control register. spi transmitter empty (spte) ? the spte bit is set every time a byte transfers from the transmit data register to the shift register. the spi transmit interrupt enable bit, sptie, enables spte cpu interrupt requests. spte is in the spi status and control register and sptie is in the spi control register. mode fault bit (modf) ? the modf bit is set in a slave spi if the ss pin goes high during a transmission with the mode fault enable bit (modfen) set. in a master spi, the modf bit is set if the ss pin goes low at any time with the modfen bit set. the error interrupt enable bit, errie, enables modf cpu interrupt requests. modf, modfen, and errie are in the spi status and control register. overflow bit (ovrf) ? the ovrf bit is set if software does not read the byte in the receive data register before the next full byte enters the shift register. the error interrupt enable bit, errie, enables ovrf cpu interrupt requests. ovrf and errie are in the spi status and control register.
resets and interrupts mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 132 freescale semiconductor 13.3.2.8 sci sci cpu interrupt sources: sci transmitter empty bit (scte) ? scte is set when the sci data register transfers a character to the transmit shift register. the sci transmit interrupt enable bit, sctie, enables transmitter cpu interrupt requests. scte is in sci status regi ster 1. sctie is in sci control register 2. transmission complete bit (tc) ? tc is set when the transmit shift register and the sci data register are empty and no break or idle characte r has been generated. the transmission complete interrupt enable bit, tcie, enables transmitter cpu interrupt requests. tc is in sci status register 1. tcie is in sci control register 2. sci receiver full bit (scrf) ? scrf is set when the receive shift register transfers a character to the sci data register. the sci receive interrupt enable bit, scrie, enables receiver cpu interrupts. scrf is in sci status register 1. scrie is in sci control register 2. idle input bit (idle) ? idle is set when 10 or 11 c onsecutive 1s shift in from the rxd pin. the idle line interrupt enable bit, ilie, enables idle cpu interrupt requests. idle is in sci status register 1. ilie is in sci control register 2. receiver overrun bit (or) ? or is set when the re ceive shift register shifts in a new character before the previous character was read from t he sci data register. the overrun interrupt enable bit, orie, enables or to generate sci error cpu inte rrupt requests. or is in sci status register 1. orie is in sci control register 3. noise flag (nf) ? nf is set when the sci detec ts noise on incoming data or break characters, including start, data, and stop bits. the noise error interrupt enable bit, neie, enables nf to generate sci error cpu interrupt requests. nf is in sci status register 1. neie is in sci control register 3. framing error bit (fe) ? fe is set when a 0 occurs where the receiver expects a stop bit. the framing error interrupt enable bit, feie, enables fe to generate sci error cpu interrupt requests. fe is in sci status register 1. feie is in sci control register 3. parity error bit (pe) ? pe is set when the sci detects a parity error in incoming data. the parity error interrupt enable bit, peie, enables pe to generate sci error cpu interrupt requests. pe is in sci status register 1. peie is in sci control register 3. 13.3.2.9 kbd0 ?kbd7 pins a falling edge on a keyboard interrupt pi n latches an external interrupt request. 13.3.2.10 adc (analog-to-digital converter) when the aien bit is set, the adc module is capable of generating a cpu interrupt after each adc conversion. the coco bit is not used as a conversion complete flag when interrupts are enabled. 13.3.2.11 tbm (timebase module) the timebase module can interrupt the cpu on a regul ar basis with a rate defined by tbr2?tbr0. when the timebase counter chain rolls over, the tbif flag is set. if the tbie bit is set, enabling the timebase interrupt, the counter chain overflow will generate a cpu interrupt request. interrupts must be acknowledged by writing a 1 to the tack bit.
interrupts mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 133 13.3.3 interrupt status registers the flags in the interrupt status registers identify maskable interrupt sources. table 13-2 summarizes the interrupt sources and the interrupt status register flags that they set. the interrupt status registers can be useful for debugging. 13.3.3.1 interrupt status register 1 if6?if1 ? interrupt flags 6?1 these flags indicate the presence of interrupt requests from the sources shown in table 13-2 . 1 = interrupt request present 0 = no interrupt request present bit 1 and bit 0 ? always read 0 table 13-2. interrupt source flags interrupt source interrupt status register flag reset ? swi instruction ? irq pin if1 cgm (pll) if2 tim1 channel 0 if3 tim1 channel 1 if4 tim1 overflow if5 tim2 channel 0 if6 tim2 channel 1 if7 tim2 overflow if8 spi receive if9 spi transmit if10 sci error if11 sci receive if12 sci transmit if13 keyboard if14 adc conversion complete if15 timebase if16 address: $fe04 bit 7654321bit 0 read: if6 if5 if4 if3 if2 if1 0 0 write:rrrrrrrr reset:00000000 r = reserved figure 13-7. interrupt status register 1 (int1)
resets and interrupts mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 134 freescale semiconductor 13.3.3.2 interrupt status register 2 if14?if7 ? interrupt flags 14?7 these flags indicate the presence of interrupt requests from the sources shown in table 13-2 . 1 = interrupt request present 0 = no interrupt request present 13.3.3.3 interrupt status register 3 if16?if15 ? interrupt flags 16?15 this flag indicates the presence of an in terrupt request from the source shown in table 13-2 . 1 = interrupt request present 0 = no interrupt request present bits 7?2 ? always read 0 address: $fe05 bit 7654321bit 0 read: if14 if13 if12 if11 if10 if9 if8 if7 write:rrrrrrrr reset:00000000 r = reserved figure 13-8. interrupt status register 2 (int2) address: $fe06 bit 7654321bit 0 read:000000if16if15 write:rrrrrrrr reset:00000000 r = reserved figure 13-9. interrupt status register 3 (int3)
mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 135 chapter 14 serial communications interface (sci) module 14.1 introduction this section describes the serial communications interface (sci) module, which allows high-speed asynchronous communications with peripheral devices and other mcus. 14.2 features features of the sci module include: full-duplex operation standard mark/space non-retu rn-to-zero (nrz) format 32 programmable baud rates programmable 8-bit or 9-bit character length separately enabled transmitter and receiver separate receiver and transmitter cpu interrupt requests programmable transmitter output polarity two receiver wakeup methods: ? idle line wakeup ? address mark wakeup interrupt-driven operation with eight interrupt flags: ? transmitter empty ? transmission complete ? receiver full ? idle receiver input ? receiver overrun ? noise error ? framing error ? parity error receiver framing error detection hardware parity checking 1/16 bit-time noise detection mask option register bit, scibdsrc, to allow selection of baud rate clock source
serial communications interface (sci) module mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 136 freescale semiconductor figure 14-1. block diagram highlighting sci block and pins single breakpoint break module clock generator module system integration module programmable timebase module monitor module serial peripheral 2-channel timer interface module 2 dual voltage low-voltage inhibit module 8-bit keyboard arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers user rom user ram monitor rom user rom vector space single external interrupt module porta ddra ddrc portc ddrd portd ddre porte internal bus osc1 osc2 cgmxfc rst (3) irq (3) interface module interrupt module computer operating properly module pta7/kbd7 ? ptb7/ad7 ptb6/ad6 ptb5/ad5 ptb4/ad4 ptb3/ad3 ptb2/ad2 ptb1/ad1 ptb0/ad0 v ddad /v refh 8-bit analog-to-digital converter module ptc6 (1) ptc5 (1) ptc4 (1, 2) ptc3 (1, 2) ptc2 (1, 2) ptc1 (1, 2) ptc0 (1, 2) ptd7/t2ch1 (1) ptd6/t2ch0 (1) ptd5/t1ch1 (1) ptd4/t1ch0 (1) ptd3/spsck (1) ptd2/mosi (1) ptd1/miso (1) ptd0/ss (1) pte1/rxd pte0/txd v ssad /v refl 2-channel timer interface module 1 32-khz oscillator phase-locked loop serial communications interface module power-on reset module memory map module mask option register 1 module security module mask option register 2 module power v ss v dd v ssa v dda 1. ports are software configurable with pullup device if input port. 2. higher current drive port pins 3. pin contains int egrated pullup device ddrb portb 64 bytes pta0/kbd0 (1) mc68hc08gp32a ? 32,256 bytes 512 bytes 307 bytes 36 bytes mc68hc08gp16a ? 15,872 bytes
pin name conventions mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 137 14.3 pin name conventions the generic names of the sci i/o pins are: rxd (receive data) txd (transmit data) sci i/o (input/output) lines are implemented by shar ing parallel i/o port pins. the full name of an sci input or output reflects the name of the shared port pin. table 14-1 shows the full names and the generic names of the sci i/o pins. the generic pin names appear in the text of this section. 14.4 functional description figure 14-3 shows the structure of the sci module. the sc i allows full-duplex, asynchronous, nrz serial communication among the mcu and remote devices, in cluding other mcus. the transmitter and receiver of the sci operate independently, although they use the same baud rate generator. during normal operation, the cpu monitors the status of the sci, writes the data to be transmitted, and processes received data. the baud rate clock source for the sci can be select ed via the configuration bit, scibdsrc, of the mor2 register ($001e). source selection values are shown in figure 14-3 . 14.4.1 data format the sci uses the standard non-return-to-zero mark/space data format illustrated in figure 14-2 . figure 14-2. sci data formats table 14-1. pin name conventions generic pin names: rxd txd full pin names: pte1/rxd pte0/txd bit 5 start bit bit 0 bit 1 next stop bit start bit 8-bit data format bit m in scc1 clear start bit bit 0 next stop bit start bit 9-bit data format bit m in scc1 set bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 2 bit 3 bit 4 bit 6 bit 7 parity bit parity bit
serial communications interface (sci) module mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 138 freescale semiconductor figure 14-3. sci module block diagram scte tc scrf idle or nf fe pe sctie tcie scrie ilie te re rwu sbk r8 t8 orie feie peie bkf rpf sci data receive shift register sci data register transmit shift register neie m wake ilty flag control transmit control receive control data selection control wakeup pty pen register transmitter interrupt control receiver interrupt control error interrupt control control ensci loops ensci internal bus txinv loops 4 16 pre- scaler baud divider cgmxclk bus clock a b sl x scibdsrc from sl = 0 => x = a sl = 1 => x = b mor2 pte0/txd pte1/rxd
functional description mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 139 14.4.2 transmitter figure 14-5 shows the structure of the sci transmitter. the baud rate clock source for the sci can be selected via the configuration bit, scibdsrc. source selection values are shown in figure 14-5 . 14.4.2.1 character length the transmitter can accommodate either 8-bit or 9-bit data. the state of the m bit in sci control register 1 (scc1) determines character length. when transmitting 9- bit data, bit t8 in sci control register 3 (scc3) is the ninth bit (bit 8). addr.register name bit 7654321bit 0 $0013 sci control register 1 (scc1) see page 150. read: loops ensci txinv m wake ilty pen pty write: reset:00000000 $0014 sci control register 2 (scc2) see page 152. read: sctie tcie scrie ilie te re rwu sbk write: reset:00000000 $0015 sci control register 3 (scc3) see page 154. read: r8 t8 r r orie neie feie peie write: reset:uu000000 $0016 sci status register 1 (scs1) see page 155. read: scte tc scrf idle or nf fe pe write: reset:11000000 $0017 sci status register 2 (scs2) see page 157. read: bkf rpf write: reset:00000000 $0018 sci data register (scdr) see page 158. read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset $0019 sci baud rate register (scbr) see page 158. read: scp1 scp0 r scr2 scr1 scr0 write: reset:00000000 = unimplemented r = reserved u = unaffected figure 14-4. sci i/o register summary
serial communications interface (sci) module mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 140 freescale semiconductor figure 14-5. sci transmitter 14.4.2.2 character transmission during an sci transmission, the transmit shift register sh ifts a character out to the pte0/txd pin. the sci data register (scdr) is the write-only buffer between the internal data bus and the transmit shift register. to initiate an sci transmission: 1. enable the sci by writing a 1 to the enable sci bit (ensci) in sci control register 1 (scc1). 2. enable the transmitter by writing a 1 to the tr ansmitter enable bit (te) in sci control register 2 (scc2). 3. clear the sci transmitter empty bit by first reading sci status register 1 (scs1) and then writing to the scdr. 4. repeat step 3 for each subsequent transmission. pen pty h876543210l 11-bit transmit stop start t8 scte sctie tcie sbk tc parity generation msb sci data register load from scdr shift enable preamble all 1s break all 0s transmitter control logic shift register tc sctie tcie scte transmitter cpu m ensci loops te pte0/txd txinv internal bus 4 pre- scaler scp1 scp0 scr1 scr2 scr0 baud divider 16 cgmxclk bus clock a b sl x sl = 0 => x = a sl = 1 => x = b scibdsrc from mor2 interrupt request
functional description mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 141 at the start of a transmission, transmitter control logi c automatically loads the tran smit shift register with a preamble of 1s. after the preamble shifts out, cont rol logic transfers the s cdr data into the transmit shift register. a 0 start bit automatically goes into t he least significant bit position of the transmit shift register. a 1 stop bit goes into t he most significant bit position. the sci transmitter empty bit, scte, in scs1 beco mes set when the scdr transfers a byte to the transmit shift register. the scte bi t indicates that the scdr can accept new data from the internal data bus. if the sci transmit interrupt enable bit, sctie, in scc2 is also set, the scte bit generates a transmitter cpu interrupt request. when the transmit shift register is not transmitting a character, the pte0/txd pin goes to the idle condition, 1. if at any time software clears the ensci bi t in sci control register 1 (scc1), the transmitter and receiver relinquish control of the port e pins. 14.4.2.3 break characters writing a 1 to the send break bit, sbk, in scc2 loads t he transmit shift register with a break character. a break character contains all 0s and has no start, st op, or parity bit. break character length depends on the m bit in scc1. as long as sbk is 1, transmitter logic continuously loads break characters into the transmit shift register. after software clears the sbk bi t, the shift register finish es transmitting the last break character and then transmits at least one 1. the automatic 1 at the end of a break character guarantees the recognition of the start bit of the next character. the sci recognizes a break character when a start bi t is followed by eight or nine 0 data bits and a 0 where the stop bit should be. receiving a break character has these effects on sci registers: sets the framing error bit (fe) in scs1 sets the sci receiver full bit (scrf) in scs1 clears the sci data register (scdr) clears the r8 bit in scc3 sets the break flag bit (bkf) in scs2 may set the overrun (or), noise flag (nf), parity error (pe), or reception in progress flag (rpf) bits 14.4.2.4 idle characters an idle character contains all 1s and has no start, st op, or parity bit. idle character length depends on the m bit in scc1. the preamble is a synchronizing idle character that begins every transmission. if the te bit is cleared during a tr ansmission, the pte0/txd pin becomes idle after completion of the transmission in progress. clearing and then setting the te bit during a transmission queues an idle character to be sent after the character currently being transmitted. note when queueing an idle character, return the te bit to 1 before the stop bit of the current character shifts out to the txd pin. setting te after the stop bit appears on txd causes data previously written to the scdr to be lost. toggle the te bit for a queued idle character when the scte bit becomes set and just before writing the next byte to the scdr.
serial communications interface (sci) module mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 142 freescale semiconductor 14.4.2.5 inversion of transmitted output the transmit inversion bit (txinv) in sci control regi ster 1 (scc1) reverses the polarity of transmitted data. all transmitted values, including idle, break, start, and stop bits, are inverted when txinv is 1. see 14.8.1 sci control register 1. 14.4.2.6 transmitter interrupts these conditions can generate cpu interrupt requests from the sci transmitter: sci transmitter empty (scte) ? the scte bit in scs1 indicates that the scdr has transferred a character to the transmit shift register. scte can generate a transmitter cpu interrupt request. setting the sci transmit interrupt enable bit, sctie, in scc2 enables the scte bit to generate transmitter cpu interrupt requests. transmission complete (tc) ? the tc bit in scs1 indicates that the transmit shift register and the scdr are empty and that no break or idle character has been generated. the transmission complete interrupt enable bit, tcie, in scc2 enables the tc bit to generate transmitter cpu interrupt requests. 14.4.3 receiver figure 14-6 shows the structure of the sci receiver. 14.4.3.1 character length the receiver can accommodate either 8-bit or 9-bit data . the state of the m bit in sci control register 1 (scc1) determines character length. when receiving 9-bi t data, bit r8 in sci control register 2 (scc2) is the ninth bit (bit 8). when receiving 8-bit data, bit r8 is a copy of the eighth bit (bit 7). 14.4.3.2 character reception during an sci reception, the receive shift register shi fts characters in from th e pte1/rxd pin. the sci data register (scdr) is the read-onl y buffer between the internal data bus and the receive shift register. after a complete character shifts into the receive sh ift register, the data portion of the character transfers to the scdr. the sci receiver full bit, scrf, in sci status register 1 (scs1) becomes set, indicating that the received byte can be read. if th e sci receive interrupt enable bit, scrie, in scc2 is also set, the scrf bit generates a receiver cpu interrupt request. 14.4.3.3 data sampling the receiver samples the pte1/rxd pin at the rt cl ock rate. the rt clock is an internal signal with a frequency 16 times the baud rate. to adjust for baud rate mismatch, the rt clock is resynchronized at the following times (see figure 14-7 ): after every start bit after the receiver detects a data bit change from 1 to 0 (after the majority of data bit samples at rt8, rt9, and rt10 returns a valid 1 and the majority of the next rt8, rt9, and rt10 samples returns a valid 0) to locate the start bit, data recovery logic does an asynchronous search for a 0 preceded by three 1s. when the falling edge of a possible start bit oc curs, the rt clock begins to count to 16.
functional description mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 143 figure 14-6. sci receiver block diagram all 0s m wake ilty pen pty bkf rpf h876543210l 11-bit receive shift register stop start data recovery or orie nf neie fe feie pe peie wakeup logic parity checking msb sci data register r8 orie neie feie peie rwu scrf idle or nf fe pe internal bus pre- scaler baud divider 4 16 scp1 scp0 scr1 scr2 scr0 cgmxclk bus clock a b sl x scibdsrc from sl = 0 => x = a sl = 1 => x = b mor2 pte1/rxd error cpu interrupt request
serial communications interface (sci) module mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 144 freescale semiconductor figure 14-7. receiver data sampling to verify the start bit and to detect noise, data recovery logic takes samples at rt3, rt5, and rt7. table 14-2 summarizes the results of the start bit verification samples. start bit verification is not successful if any two of the three verification samples are 1s. if start bit verification is not successful, the rt clock is reset and a new search for a start bit begins. to determine the value of a data bit and to detect noise, recovery logic takes samples at rt8, rt9, and rt10. table 14-3 summarizes the results of the data bit samples. table 14-2. start bit verification rt3, rt5, and rt7 samples start bit verification noise flag 000 yes 0 001 yes 1 010 yes 1 011 no 0 100 yes 1 101 no 0 110 no 0 111 no 0 table 14-3. data bit recovery rt8, rt9, and rt10 samples data bit determination noise flag 000 0 0 001 0 1 010 0 1 011 1 1 rt clock reset rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt5 rt8 rt7 rt6 rt11 rt10 rt9 rt15 rt14 rt13 rt12 rt16 rt1 rt2 rt3 rt4 start bit qualification start bit verification data sampling samples rt clock rt clock state start bit lsb pte1/rxd
functional description mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 145 note the rt8, rt9, and rt10 samples do not affect start bit verification. if any or all of the rt8, rt9, and rt10 start bit samples are 1s following a successful start bit verification, the noi se flag (nf) is set and the receiver assumes that the bit is a start bit. to verify a stop bit and to detect noise, recovery logic takes samples at rt8, rt9, and rt10. table 14-4 summarizes the results of the stop bit samples. 14.4.3.4 framing errors if the data recovery logic does not detect a 1 where t he stop bit should be in an incoming character, it sets the framing error bit, fe, in scs1. a break character also sets the fe bit because a break character has no stop bit. the fe bit is set at the same time that the scrf bit is set. 14.4.3.5 baud rate tolerance a transmitting device may be operating at a baud rate below or above the receiver baud rate. accumulated bit time misalignment can cause one of the three stop bi t data samples to fall outside the actual stop bit. then a noise error occurs. if more than one of the samples is outside the stop bit, a framing error occurs. in most applications, the baud rate tolerance is much more than the degree of misalignment that is likely to occur. as the receiver samples an incoming character, it resynchronizes the rt clock on any valid falling edge within the character. resynchronization within char acters corrects misalignments between transmitter bit times and receiver bit times. 100 0 1 101 1 1 110 1 1 111 1 0 table 14-4. stop bit recovery rt8, rt9, and rt10 samples framing error flag noise flag 000 1 0 001 1 1 010 1 1 011 0 1 100 1 1 101 0 1 110 0 1 111 0 0 table 14-3. data bit recovery (continued) rt8, rt9, and rt10 samples data bit determination noise flag
serial communications interface (sci) module mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 146 freescale semiconductor slow data tolerance figure 14-8 shows how much a slow receiv ed character can be misaligned without causing a noise error or a framing error. the slow stop bit begins at rt8 inst ead of rt1 but arrives in time for the stop bit data samples at rt8, rt9, and rt10. for an 8-bit character, data sampling of the stop bit takes the receiver 9 bit times 16 rt cycles + 10 rt cycles = 154 rt cycles. with the misaligned character shown in figure 14-8 , the receiver counts 154 rt cycles at the point when the count of the transmitti ng device is 9 bit times 16 rt cycles + 3 rt cycles = 147 rt cycles. figure 14-8. slow data the maximum percent difference between the receiver count and the transmitter count of a slow 8-bit character with no errors is for a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times 16 rt cycles + 10 rt cycles = 170 rt cycles. with the misaligned character shown in figure 14-8 , the receiver counts 170 rt cycles at the point when the count of the transmitting device is 10 bit times 16 rt cycles + 3 rt cycles = 163 rt cycles. the maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is fast data tolerance figure 14-9 shows how much a fast received character can be misaligned without causing a noise error or a framing error. the fast stop bit ends at rt10 instead of rt16 but is still there for the stop bit data samples at rt8, rt9, and rt10. figure 14-9. fast data msb stop rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt11 rt12 rt13 rt14 rt15 rt16 data samples receiver rt clock 154 147 ? 154 ------------------------- - 100 4.54% = 170 163 ? 170 ------------------------- - 100 4.12% = idle or next character stop rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt11 rt12 rt13 rt14 rt15 rt16 data samples receiver rt clock
functional description mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 147 for an 8-bit character, data sampling of the stop bit takes the receiver 9bittimes 16 rt cycles + 10 rt cycles = 154 rt cycles. with the misaligned character shown in figure 14-9 , the receiver counts 154 rt cycles at the point when the count of the transmitting device is 10 bit times 16 rt cycles = 160 rt cycles. the maximum percent difference between the receiver count and the transmitter count of a fast 8-bit character with no errors is for a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times 16 rt cycles + 10 rt cycles = 170 rt cycles. with the misaligned character shown in figure 14-9 , the receiver counts 170 rt cycles at the point when the count of the transmitting device is 11 bit times 16 rt cycles = 176 rt cycles. the maximum percent difference between the receiver count and the transmitter count of a fast 9-bit character with no errors is 14.4.3.6 receiver wakeup so that the mcu can ignore transmissions intended only for other receivers in multiple-receiver systems, the receiver can be put into a standby state. setting the receiver wakeup bit, rwu, in scc2 puts the receiver into a standby state during which receiver interrupts are disabled. depending on the state of the wake bit in scc1, either of two conditions on the pte1/rxd pin can bring the receiver out of the standby state: address mark ? an address mark is a 1 in the most significant bit position of a received character. when the wake bit is set, an address mark wakes th e receiver from the standby state by clearing the rwu bit. the address mark also sets the sc i receiver full bit, scrf. software can then compare the character containing the address mark to the user-defined address of the receiver. if they are the same, the receiver remains awake and processes the characters that follow. if they are not the same, software can set the rwu bit and put the receiver back into the standby state. idle input line condition ? when the wake bit is cl ear, an idle character on the pte1/rxd pin wakes the receiver from the standby state by clearing the rwu bit. the idle character that wakes the receiver does not set the receiver idle bit, idle, or the sci receiver full bit, scrf. the idle line type bit, ilty, determines whether the receiver begins counting 1s as idle character bits after the start bit or after the stop bit. note with the wake bit clear, setting the rwu bit after the rxd pin has been idle may cause the receiver to wake up immediately. 154 160 ? 154 ------------------------- - 100 3.90% = 170 176 ? 170 ------------------------- - 100 3.53% =
serial communications interface (sci) module mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 148 freescale semiconductor 14.4.3.7 receiver interrupts the following sources can generate cpu interrupt requests from the sci receiver: sci receiver full (scrf) ? the scrf bit in scs1 indicates that the receive shift register has transferred a character to the scdr. scrf can generate a receiver cpu interrupt request. setting the sci receive interrupt enable bit, scrie, in scc2 enables the scrf bit to generate receiver cpu interrupts. idle input (idle) ? the idle bit in scs1 indicates that 10 or 11 consecutive 1s shifted in from the pte1/rxd pin. the idle line interrupt enable bit, ilie, in scc2 enables the idle bit to generate cpu interrupt requests. 14.4.3.8 error interrupts the following receiver error flags in scs1 can generate cpu interrupt requests: receiver overrun (or) ? the or bit indicates t hat the receive shift register shifted in a new character before the previous c haracter was read from the scdr. the previous character remains in the scdr, and the new character is lost. th e overrun interrupt enable bit, orie, in scc3 enables or to generate sci error cpu interrupt requests. noise flag (nf) ? the nf bit is set when t he sci detects noise on incoming data or break characters, including start, data, and stop bits. the noise error interrupt enable bit, neie, in scc3 enables nf to generate sci error cpu interrupt requests. framing error (fe) ? the fe bit in scs1 is set when a 0 occurs where the receiver expects a stop bit. the framing error interrupt enable bit, feie, in scc3 enables fe to generate sci error cpu interrupt requests. parity error (pe) ? the pe bit in scs1 is set when the sci detects a parity error in incoming data. the parity error interrupt enable bit, peie, in s cc3 enables pe to generate sci error cpu interrupt requests. 14.5 low-power modes the wait and stop instructions put the mcu in low power- consumption standby modes. 14.5.1 wait mode the sci module remains active after the execution of a wait instruction. in wait mode, the sci module registers are not accessible by the cpu. any enabl ed cpu interrupt request from the sci module can bring the mcu out of wait mode. if sci module functions are not required during wait mode, reduce power consumption by disabling the module before executing the wait instruction. refer to chapter 9 low-power modes for information on exiting wait mode. 14.5.2 stop mode the sci module is inactive after the execution of a stop instruction. the stop instruction does not affect sci register states. sci module operation resumes after an external interrupt. because the internal clock is inactive during st op mode, entering stop mode during an sci transmission or reception results in invalid data. refer to chapter 9 low-power modes for information on exiting stop mode.
sci during break module interrupts mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 149 14.6 sci during br eak module interrupts the system integration module (sim) controls whethe r status bits in other modules can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bits during the break state. to allow software to clear status bits during a break in terrupt, write a 1 to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break state, write a 0 to the bcfe bit. with bcfe at 0 (its default state), software can read and write i/o registers during the brea k state without affecting status bits. some status bits have a 2-step read/write clearing procedure. if so ftware does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is at 0. after the break, doing the second step clears the status bit. 14.7 i/o signals port e shares two of its pins with the sci module. the two sci i/o pins are: pte0/txd ? transmit data pte1/rxd ? receive data 14.7.1 pte0/txd (transmit data) the pte0/txd pin is the serial data output from t he sci transmitter. the sci shares the pte0/txd pin with port e. when the sci is enabled , the pte0/txd pin is an output re gardless of the state of the ddre0 bit in data direction register e (ddre). 14.7.2 pte1/rxd (receive data) the pte1/rxd pin is the serial data input to the sci receiver. the sci shares the pte1/rxd pin with port e. when the sci is enabled, the pte1/rxd pin is an i nput regardless of the state of the ddre1 bit in data direction register e (ddre). 14.8 i/o registers these i/o registers control and monitor sci operation: sci control register 1 (scc1) sci control register 2 (scc2) sci control register 3 (scc3) sci status register 1 (scs1) sci status register 2 (scs2) sci data register (scdr) sci baud rate register (scbr)
serial communications interface (sci) module mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 150 freescale semiconductor 14.8.1 sci cont rol register 1 sci control register 1: enables loop mode operation enables the sci controls output polarity controls character length controls sci wakeup method controls idle character detection enables parity function controls parity type loops ? loop mode select bit this read/write bit enables loop mode operation. in loop mode the pte1/rxd pin is disconnected from the sci, and the transmitter output goes into the rece iver input. both the trans mitter and the receiver must be enabled to use loop mode. reset clears the loops bit. 1 = loop mode enabled 0 = normal operation enabled ensci ? enable sci bit this read/write bit enables the sci and the sci baud rate generator. clearing ensci sets the scte and tc bits in sci status register 1 and disables transmitter interrupts. reset clears the ensci bit. 1 = sci enabled 0 = sci disabled txinv ? transmit inversion bit this read/write bit reverses the polarity of transmitted data. reset clears the txinv bit. 1 = transmitter output inverted 0 = transmitter output not inverted note setting the txinv bit inverts all tran smitted values, including idle, break, start, and stop bits. m ? mode (character length) bit this read/write bit determines whether sci characters are eight or nine bits long. see table 14-5. the ninth bit can serve as an extra stop bit, as a receiver wakeup signal, or as a parity bit. reset clears the m bit. 1 = 9-bit sci characters 0 = 8-bit sci characters address: $0013 bit 7654321bit 0 read: loops ensci txinv m wake ilty pen pty write: reset:00000000 figure 14-10. sci control register 1 (scc1)
i/o registers mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 151 wake ? wakeup condition bit this read/write bit determines which condition wa kes up the sci: a 1 (address mark) in the most significant bit position of a received character or an idle condition on the pte1/rxd pin. reset clears the wake bit. 1 = address mark wakeup 0 = idle line wakeup ilty ? idle line type bit this read/write bit determines when the sci starts counting 1s as idle character bits. the counting begins either after the start bit or after the stop bi t. if the count begins after the start bit, then a string of 1s preceding the stop bit may cause false recognit ion of an idle character. beginning the count after the stop bit avoids false idle character recognition , but requires properly synchronized transmissions. reset clears the ilty bit. 1 = idle character bit count begins after stop bit 0 = idle character bit count begins after start bit pen ? parity enable bit this read/write bit enables the sci parity function. see table 14-5. when enabled, the parity function inserts a parity bit in the most significant bit position. see figure 14-2 . reset clears the pen bit. 1 = parity function enabled 0 = parity function disabled pty ? parity bit this read/write bit determines whether the sci generates and checks for odd parity or even parity. see table 14-5. reset clears the pty bit. 1 = odd parity 0 = even parity note changing the pty bit in the middle of a transmission or reception can generate a parity error. table 14-5. character format selection control bits character format m pen and pty start bits data bits parity stop bits character length 0 0x 1 8 none 1 10 bits 1 0x 1 9 none 1 11 bits 0 10 1 7 even 1 10 bits 0 11 1 7 odd 1 10 bits 1 10 1 8 even 1 11 bits 1 11 1 8 odd 1 11 bits
serial communications interface (sci) module mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 152 freescale semiconductor 14.8.2 sci cont rol register 2 sci control register 2: enables the following cpu interrupt requests: ? enables the scte bit to generate transmitter cpu interrupt requests ? enables the tc bit to generate transmitter cpu interrupt requests ? enables the scrf bit to generate receiver cpu interrupt requests ? enables the idle bit to generate receiver cpu interrupt requests enables the transmitter enables the receiver enables sci wakeup transmits sci break characters sctie ? sci transmit interrupt enable bit this read/write bit enables the scte bit to generate sci transmitter cpu interrupt requests. reset clears the sctie bit. 1 = scte enabled to generate cpu interrupt 0 = scte not enabled to generate cpu interrupt tcie ? transmission complete interrupt enable bit this read/write bit enables the tc bit to generate sci transmitter cpu interrupt requests. reset clears the tcie bit. 1 = tc enabled to generate cpu interrupt requests 0 = tc not enabled to generate cpu interrupt requests scrie ? sci receive interrupt enable bit this read/write bit enables the scrf bit to generate sci receiver cpu interrupt requests. reset clears the scrie bit. 1 = scrf enabled to generate cpu interrupt 0 = scrf not enabled to generate cpu interrupt ilie ? idle line interrupt enable bit this read/write bit enables the idle bit to generate sci receiver cpu interrupt requests. reset clears the ilie bit. 1 = idle enabled to generate cpu interrupt requests 0 = idle not enabled to generate cpu interrupt requests address: $0014 bit 7654321bit 0 read: sctie tcie scrie ilie te re rwu sbk write: reset:00000000 figure 14-11. sci control register 2 (scc2)
i/o registers mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 153 te ? transmitter enable bit setting this read/write bit begins the transmission by sending a preamble of 10 or 11 1s from the transmit shift register to the pte0/txd pin. if so ftware clears the te bit, the transmitter completes any transmission in progress before the pte0/txd returns to the idle condition (1). clearing and then setting te during a transmission queues an idle characte r to be sent after the character currently being transmitted. reset clears the te bit. 1 = transmitter enabled 0 = transmitter disabled note writing to the te bit is not allowed when the enable sci bit (ensci) is clear. ensci is in sci control register 1. re ? receiver enable bit setting this read/write bit enables the receiver. clea ring the re bit disables the receiver but does not affect receiver interrupt flag bits. reset clears the re bit. 1 = receiver enabled 0 = receiver disabled note writing to the re bit is not allowe d when the enable sci bit (ensci) is clear. ensci is in sci control register 1. rwu ? receiver wakeup bit this read/write bit puts the receiver in a standby state during which receiver interrupts are disabled. the wake bit in scc1 determines whether an idle i nput or an address mark brings the receiver out of the standby state and clears the rwu bit. reset clears the rwu bit. 1 = standby state 0 = normal operation sbk ? send break bit setting and then clearing this read/writ e bit transmits a break character followed by a 1. the 1 after the break character guarantees recogni tion of a valid start bit. if sbk remains set, the transmitter continuously transmits break c haracters with no 1s between them. reset clears the sbk bit. 1 = transmit break characters 0 = no break characters being transmitted note do not toggle the sbk bit immediately a fter setting the scte bit. toggling sbk before the preamble begins causes the sci to send a break character instead of a preamble.
serial communications interface (sci) module mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 154 freescale semiconductor 14.8.3 sci cont rol register 3 sci control register 3: stores the ninth sci data bit received and the ninth sci data bit to be transmitted enables these interrupts: ? receiver overrun interrupts ? noise error interrupts ? framing error interrupts parity error interrupts r8 ? received bit 8 when the sci is receiving 9-bit characters, r8 is the re ad-only ninth bit (bit 8) of the received character. r8 is received at the same time that the scdr receives the other 8 bits. when the sci is receiving 8-bit characters, r8 is a co py of the eighth bit (bit 7). reset has no effect on the r8 bit. t8 ? transmitted bit 8 when the sci is transmitting 9-bit characters, t8 is the read/write ninth bit (bit 8) of the transmitted character. t8 is loaded into the transmit shift regi ster at the same time that the scdr is loaded into the transmit shift register. rese t has no effect on the t8 bit. orie ? receiver overrun interrupt enable bit this read/write bit enables sci error cpu interrupt requests generated by the receiver overrun bit, or. 1 = sci error cpu interrupt requests from or bit enabled 0 = sci error cpu interrupt r equests from or bit disabled neie ? receiver noise error interrupt enable bit this read/write bit enables sci error cpu interrupt requests generated by the noise error bit, ne. reset clears neie. 1 = sci error cpu interrupt requests from ne bit enabled 0 = sci error cpu interrupt requests from ne bit disabled feie ? receiver framing error interrupt enable bit this read/write bit enables sci error cpu interrupt requests generated by the framing error bit, fe. reset clears feie. 1 = sci error cpu interrupt requests from fe bit enabled 0 = sci error cpu interrupt requests from fe bit disabled peie ? receiver parity error interrupt enable bit this read/write bit enables sci error cpu interrupt requests generated by the parity error bit, pe. see 14.8.4 sci status register 1 . reset clears peie. 1 = sci error cpu interrupt requests from pe bit enabled 0 = sci error cpu interrupt requests from pe bit disabled address: $0015 bit 7654321bit 0 read: r8 t8 r r orie neie feie peie write: reset:uu000000 = unimplemented r = reserved u = unaffected figure 14-12. sci control register 3 (scc3)
i/o registers mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 155 14.8.4 sci status register 1 sci status register 1 (scs1) contai ns flags to signal these conditions: transfer of scdr data to transmit shift register complete transmission complete transfer of receive shift register data to scdr complete receiver input idle receiver overrun noisy data framing error parity error scte ? sci transmitter empty bit this clearable, read-only bit is set when the scdr tr ansfers a character to the transmit shift register. scte can generate an sci transmitter cpu interrupt request. when the sctie bit in scc2 is set, scte generates an sci transmitter cpu interrupt reques t. in normal operation, clear the scte bit by reading scs1 with scte set and then wr iting to scdr. reset sets the scte bit. 1 = scdr data transferred to transmit shift register 0 = scdr data not transferred to transmit shift register tc ? transmission complete bit this read-only bit is set when the scte bit is se t, and no data, preamble, or break character is being transmitted. tc generates an sci transmitter cpu interrupt request if the tcie bit in scc2 is also set. tc is automatically cleared when data, preamble or break is queued and ready to be sent. there may be up to 1.5 transmitter clocks of latency be tween queueing data, preamble, and break and the transmission actually starti ng. reset sets the tc bit. 1 = no transmission in progress 0 = transmission in progress scrf ? sci receiver full bit this clearable, read-only bit is set when the data in the receive shift register transfers to the sci data register. scrf can generate an sci receiver cpu interrupt request. when the scrie bit in scc2 is set, scrf generates a cpu interrupt request. in normal operation, clear the scrf bit by reading scs1 with scrf set and then reading the scdr. reset clears scrf. 1 = received data available in scdr 0 = data not available in scdr address: $0016 bit 7654321bit 0 read: scte tc scrf idle or nf fe pe write: reset:11000000 = unimplemented figure 14-13. sci status register 1 (scs1)
serial communications interface (sci) module mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 156 freescale semiconductor idle ? receiver idle bit this clearable, read-only bit is set when 10 or 11 consecutive 1s appear on the receiver input. idle generates an sci receiver cpu interrupt request if the ilie bit in scc2 is also set. clear the idle bit by reading scs1 with idle set and then reading the scdr. after the receiver is enabled, it must receive a valid character that sets the scrf bit befo re an idle condition can set the idle bit. also, after the idle bit has been cleared, a valid character mu st again set the scrf bit before an idle condition can set the idle bit. reset clears the idle bit. 1 = receiver input idle 0 = receiver input active (or id le since the idle bit was cleared) or ? receiver overrun bit this clearable, read-only bit is set when software fails to read the scdr before the receive shift register receives the next character. the or bit generates an sci error cpu interrupt request if the orie bit in scc3 is also set. the da ta in the shift register is lost, but the data already in the scdr is not affected. clear the or bit by reading scs1 with or set and then reading the scdr. reset clears the or bit. 1 = receive shift register full and scrf = 1 0 = no receiver overrun software latency may allow an ove rrun to occur between reads of sc s1 and scdr in the flag-clearing sequence. figure 14-14 shows the normal flag-clearing sequence and an example of an overrun caused by a delayed flag-clearin g sequence. the delayed read of scdr does not clear the or bit because or was not set when scs1 was read. byte 2 caused the overrun and is lost. the next flag-clearing sequence reads byte 3 in the scdr instead of byte 2. in applications that are subject to software latency or in which it is important to know which byte is lost due to an overrun, the flag-clearing routine can check the or bit in a second read of scs1 after reading the data register. nf ? receiver noise flag bit this clearable, read-only bit is set when the sci det ects noise on the pte1/rxd pin. nf generates an sci error cpu interrupt request if the neie bit in s cc3 is also set. clear the nf bit by reading scs1 and then reading the scdr. reset clears the nf bit. 1 = noise detected 0 = no noise detected fe ? receiver framing error bit this clearable, read-only bit is set when a 0 is accepted as the stop bit. fe generates an sci error cpu interrupt request if the feie bit in scc3 also is se t. clear the fe bit by reading scs1 with fe set and then reading the scdr. reset clears the fe bit. 1 = framing error detected 0 = no framing error detected pe ? receiver parity error bit this clearable, read-only bit is set when the sci detects a parity error in incoming data. pe generates an sci error cpu interrupt request if the peie bit in scc3 is also set. clear the pe bit by reading scs1 with pe set and then reading the scdr. reset clears the pe bit. 1 = parity error detected 0 = no parity error detected
i/o registers mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 157 figure 14-14. flag clearing sequence 14.8.5 sci status register 2 sci status register 2 contains flags to signal the following conditions: break character detected incoming data bkf ? break flag bit this clearable, read-only bit is set when the sci detects a break character on the pte1/rxd pin. in scs1, the fe and scrf bits are also set. in 9-bit character transmissions, the r8 bit in scc3 is cleared. bkf does not generate a cpu interrupt request. clear bkf by reading scs2 with bkf set and then reading the scdr. once cleared, bkf can become set agai n only after 1s again appear on the pte1/rxd pin followed by another br eak character. reset clears the bkf bit. 1 = break character detected 0 = no break character detected address: $0017 bit 7654321bit 0 read: bkf rpf write: reset:00000000 = unimplemented figure 14-15. sci status register 2 (scs2) byte 1 normal flag clearing sequence read scs1 scrf = 1 read scdr byte 1 scrf = 1 scrf = 1 byte 2 byte 3 byte 4 or = 0 read scs1 scrf = 1 or = 0 read scdr byte 2 scrf = 0 read scs1 scrf = 1 or = 0 scrf = 1 scrf = 0 read scdr byte 3 scrf = 0 byte 1 read scs1 scrf = 1 read scdr byte 1 scrf = 1 scrf = 1 byte 2 byte 3 byte 4 or = 0 read scs1 scrf = 1 or = 1 read scdr byte 3 delayed flag clearing sequence or = 1 scrf = 1 or = 1 scrf = 0 or = 1 scrf = 0 or = 0
serial communications interface (sci) module mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 158 freescale semiconductor rpf ? reception in progress flag bit this read-only bit is set when the receiver detects a 0 during the rt1 time period of the start bit search. rpf does not generate an interrupt request. rpf is reset after the receiver detects false start bits (usually from noise or a baud rate mismatch) or w hen the receiver detects an idle character. polling rpf before disabling the sci module or entering st op mode can show whether a reception is in progress. 1 = reception in progress 0 = no reception in progress 14.8.6 sci data register the sci data register (scdr) is the buffer between the internal data bus and the receive and transmit shift registers. reset has no effect on data in the sci data register. r7/t7?r0/t0 ? receive/transmit data bits reading the scdr accesses the re ad-only received data bits, r7:r0. writing to the scdr writes the data to be transmitted, t7:t0. reset has no effect on the scdr. note do not use read/modify/write instructions on the sci data register. 14.8.7 sci baud rate register the baud rate register (scbr) selects the baud rate for both the receiver and the transmitter. scp1 and scp0 ? sci baud rate prescaler bits these read/write bits select the baud rate prescaler divisor as shown in table 14-6 . reset clears scp1 and scp0. address: $0018 bit 7654321bit 0 read:r7r6r5r4r3r2r1r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset figure 14-16. sci data register (scdr) address: $0019 bit 7654321bit 0 read: scp1 scp0 r scr2 scr1 scr0 write: reset:00000000 = unimplemented r = reserved figure 14-17. sci baud rate register (scbr)
i/o registers mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 159 scr2?scr0 ? sci baud rate select bits these read/write bits select the sci baud rate divisor as shown in table 14-7 . reset clears scr2?scr0. use this formula to calculate the sci baud rate: where: sci clock source = f bus or cgmxclk (selected by scibdsrc bit in mor2) pd = prescaler divisor bd = baud rate divisor table 14-8 shows the sci baud rates that can be generated with a 4.9152-mhz bus clock when f bus is selected as sci clock source. table 14-6. sci baud rate prescaling scp1 and scp0 prescaler divisor (pd) 00 1 01 3 10 4 11 13 table 14-7. sci baud rate selection scr2, scr1, and scr0 baud rate divisor (bd) 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 baud rate sci clock source 64 pd bd -------------------------------------------- - =
serial communications interface (sci) module mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 160 freescale semiconductor table 14-8. sci baud rate selection examples scp1 and scp0 prescaler divisor (pd) scr2, scr1, and scr0 baud rate divisor (bd) baud rate (f bus = 4.9152 mhz) 00 1 000 1 76,800 00 1 001 2 38,400 00 1 010 4 19,200 00 1 011 8 9600 00 1 100 16 4800 00 1 101 32 2400 00 1 110 64 1200 00 1 111 128 600 01 3 000 1 25,600 01 3 001 2 12,800 01 3 010 4 6400 01 3 011 8 3200 01 3 100 16 1600 01 3 101 32 800 01 3 110 64 400 01 3 111 128 200 10 4 000 1 19,200 10 4 001 2 9600 10 4 010 4 4800 10 4 011 8 2400 10 4 100 16 1200 10 4 101 32 600 10 4 110 64 300 10 4 111 128 150 11 13 000 1 5908 11 13 001 2 2954 11 13 010 4 1477 11 13 011 8 739 11 13 100 16 369 11 13 101 32 185 11 13 110 64 92 11 13 111 128 46
mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 161 chapter 15 system integration module (sim) 15.1 introduction this section describes the system integration module (sim). together with the cpu, the sim controls all mcu activities. a block diagram of the sim is shown in figure 15-1 . table 15-1 is a summary of the sim input/output (i/o) registers. the sim is a system state controller that coordinates cpu and exception timing. the sim is responsible for: bus clock generation and control for cpu and peripherals: ? stop/wait/reset/break entry and recovery ? internal clock control master reset control, including power-on reset (por) and cop timeout interrupt arbitration table 15-1 shows the internal signal names used in this section. table 15-1. signal name conventions signal name description cgmxclk buffered version of osc1 from clock generator module (cgm) cgmvclk pll output cgmout pll-based or osc1-based clock output from cgm module (bus clock = cgmout divided by two) iab internal address bus idb internal data bus porrst signal from the power- on reset module to the sim irst internal reset signal r/w read/write signal
system integration module (sim) mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 162 freescale semiconductor figure 15-1. sim block diagram addr. register name bit 7 6 5 4 3 2 1 bit 0 $fe00 sim break status register (sbsr) see page 175. read: rrrrrr sbsw r write: note reset: 0 note: writing a 0 clears sbsw. $fe01 sim reset status register (srsr) see page 176. read: por pin cop ilop ilad 0 lvi 0 write: por:10000000 $fe02 reserved rrrrrrrr $fe03 sim break flag control register (sbfcr) see page 177. read: bcferrrrrrr write: reset: 0 figure 15-2. sim i/o register summary stop/wait clock control clock generators por control reset pin control sim reset status register interrupt control and priority decode module stop module wait cpu stop (from cpu) cpu wait (from cpu) simoscen (to cgm) cgmout (from cgm) internal clocks master reset control reset pin logic lvi (from lvi module) illegal opcode (from cpu) illegal address (from address map decoders) cop (from cop module) interrupt sources cpu interface reset control sim counter cop clock cgmxclk (from cgm) 2 v dd internal pullup device
sim bus clock control and generation mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 163 15.2 sim bus clock control and generation the bus clock generator provides system clock signa ls for the cpu and peripherals on the mcu. the system clocks are generated from an in coming clock, cgmout, as shown in figure 15-3 . this clock can come from either an external osc illator or from the on-chip pll. (see chapter 4 clock generator module (cgm) .) figure 15-3. cgm clock signals 15.2.1 bus timing in user mode , the internal bus frequency is either the crys tal oscillator output (cgmxclk) divided by four or the pll output (cgmvclk) divided by four. $fe04 interrupt status register 1 (int1) see page 171. read: if6 if5 if4 if3 if2 if1 0 0 write:rrrrrrrr reset:00000000 $fe05 interrupt status register 2 (int2) see page 172. read: if14 if13 if12 if11 if10 if9 if8 if7 write:rrrrrrrr reset:00000000 $fe06 interrupt status register 3 (int3) see page 172. read: 0 0 0 0 0 0 if16 if15 write:rrrrrrrr reset:00000000 = unimplemented addr. register name bit 7 6 5 4 3 2 1 bit 0 figure 15-2. sim i/o register summary (continued) 2 bus clock generators sim sim counter monitor mode user mode simoscen oscillator (osc) osc2 osc1 phase-locked loop (pll) cgmxclk cgmrclk it12 cgmout simdiv2 ptc3 to timtb15a, adc oscstopenb from mor to rest of chip it23 to rest of chip
system integration module (sim) mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 164 freescale semiconductor 15.2.2 clock startup fr om por or lvi reset when the power-on reset module or the low-voltage inhibit module generates a reset, the clocks to the cpu and peripherals are inactive and held in an inac tive phase until after the 4096 cgmxclk cycle por timeout has completed. the rst pin is driven low by the sim during this entire period. the bus clocks start upon completion of the timeout. 15.2.3 clocks in stop mode and wait mode upon exit from stop mode by an interrupt, break, or reset, the sim allows cgmxclk to clock the sim counter. the cpu and peripheral clocks do not become active until after the stop delay timeout. this timeout is selectable as 4096 or 32 cgmxclk cycles. (see 15.6.2 stop mode .) in wait mode, the cpu clocks are inactive. the sim also produces two sets of clocks for other modules. refer to the wait mode subsection of each module to s ee if the module is active or inactive in wait mode. some modules can be programmed to be active in wait mode. 15.3 reset and s ystem initialization the mcu has these reset sources: power-on reset module (por) external reset pin (rst ) computer operating properly module (cop) low-voltage inhibit module (lvi) illegal opcode illegal address all of these resets produce the vector $fffe:$ffff ($fefe:$feff in monitor mode) and assert the internal reset signal (irst). irst causes all register s to be returned to their default values and all modules to be returned to their reset states. an internal reset clears the sim counter (see 15.4 sim counter ), but an external reset does not. each of the resets sets a corresponding bit in the sim reset status register (srsr). (see 15.7 sim registers .) 15.3.1 external pin reset the rst pin circuit includes an internal pullu p device. pulling the asynchronous rst pin low halts all processing. the pin bit of the sim reset status register (srsr) is set as long as rst is held low for at least the minimum t rl time and no other reset sources are present. figure 15-4 shows the relative timing. figure 15-4. external reset timing rst iab pc vect h vect l cgmout
reset and system initialization mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 165 15.3.2 active resets from internal sources all internal reset sources actively pull the rst pin low for 32 cgmxclk cycles to allow resetting of external peripherals. the internal reset signal conti nues to be asserted for an additional 32 cycles. see figure 15-5 . an internal reset can be caused by an illegal address, illegal opcode, cop timeout, lvi, or por. (see figure 15-6 .) note for lvi or por resets, the sim c ycles through 4096 cgmxclk cycles during which the sim forces the rst pin low. the internal reset signal then follows the sequence from the falling edge of rst shown in figure 15-5 . figure 15-5. internal reset timing the cop reset is asynchronous to the bus clock. figure 15-6. sources of internal reset the active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the mcu. 15.3.2.1 power-on reset when power is first applied to the mcu, the power-on reset module (por) generates a pulse to indicate that power-on has occurred. the external reset pin (rst ) is held low while the sim counter counts out 4096 + 32 cgmxclk cycles. thirty-two cgmxclk cycles later, the cpu and memories are released from reset to allow the reset vector sequence to occur. table 15-2. reset recovery reset recovery type actual number of cycles por/lvi 4163 (4096 + 64 + 3) all others 67 (64 + 3) irst rst rst pulled low by mcu iab 32 cycles 32 cycles vector high cgmxclk illegal address rst illegal opcode rst coprst lvi por internal reset
system integration module (sim) mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 166 freescale semiconductor at power-on, these events occur: a por pulse is generated. the internal reset signal is asserted. the sim enables cgmout. internal clocks to the cpu and modules are hel d inactive for 4096 cgmxclk cycles to allow stabilization of the oscillator. the rst pin is driven low during the oscillator stabilization time. the por bit of the sim reset status register (srsr) is set figure 15-7. por recovery 15.3.2.2 computer operating properly (cop) reset an input to the sim is reserved for the cop reset signal. the overflow of th e cop counter causes an internal reset and sets the cop bit in the sim reset status register (srsr). the sim actively pulls down the rst pin for all internal reset sources. to prevent a cop module timeout, write any value to location $ffff. writing to location $ffff clears the cop counter and bits 12 through 5 of the sim coun ter. the sim counter output, which occurs at least every 2 13 ? 2 4 cgmxclk cycles, drives the cop counter. the cop should be serviced as soon as possible out of reset to guarantee the maximu m amount of time before the first timeout. the cop module is disabled if the rst pin or the irq pin is held at v tst while the mcu is in monitor mode. the cop module can be disabled only through combinational logic conditioned with the high voltage signal on the rst or the irq pin. this prevents the cop from becoming disabled as a result of external noise. during a break state, v tst on the rst pin disables the cop module. porrst osc1 cgmxclk cgmout rst iab 4096 cycles 32 cycles 32 cycles $fffe $ffff irst
sim counter mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 167 15.3.2.3 illegal opcode reset the sim decodes signals from the cpu to detect illegal instructions. an illegal instruction sets the ilop bit in the sim reset status register (srsr) and causes a reset. if the stop enable bit, stop, in the mask option register is 0, the sim treats the stop instruction as an illegal opcode and causes an illegal opcode re set. the sim actively pulls down the rst pin for all internal reset sources. 15.3.2.4 illegal address reset an opcode fetch from an unmapped address generates an illegal address reset. the sim verifies that the cpu is fetching an opcode prior to asserting the ilad bit in the sim reset status register (srsr) and resetting the mcu. a data fetch from an unmapped add ress does not generate a reset. the sim actively pulls down the rst pin for all internal reset sources. 15.3.2.5 low-voltage inhibit (lvi) reset the low-voltage inhibit module (lvi) asserts its output to the sim when the v dd voltage falls to the v tripf voltage. the lvi bit in the sim reset status register (srsr) is set, and the external reset pin (rst ) is held low if the lvipwrd and lvirstd bits in the mask option register are 0. the rst pin will be held low while the sim counter counts out 4096 + 32 cgmxclk cycles after v dd rises above v tripr . thirty-two cgmxclk cycles later, the cpu is released from rese t to allow the reset vector sequence to occur. the sim actively pulls down the rst pin for all internal reset sources. 15.4 sim counter the sim counter is used by the power-on reset module (por) and in stop mode recovery to allow the oscillator time to stabilize before enabling the inter nal bus clocks. the sim counter also serves as a prescaler for the computer operating properly module (cop). the sim counter overflow supplies the clock for the cop module. the si m counter is 12 bits long. 15.4.1 sim counter du ring power-on reset the power-on reset module (por) detects power applied to the mcu. at power-on, the por circuit asserts the signal porrst. once the sim is initializ ed, it enables the clock generation module (cgm) to drive the bus clock state machine. 15.4.2 sim counter du ring stop mode recovery the sim counter also is used for stop mode recovery. the stop instruction clears the sim counter. after an interrupt, break, or reset, the sim senses the state of the short stop recovery bit, ssrec, in the mask option register. if the ssrec bit is a 1, then the stop recovery is reduced from the normal delay of 4096 cgmxclk cycles down to 32 cgmxclk cycles. this is ideal for applications using crystals with the oscstopenb bit set. external crystal applications should use the full stop recovery time, ssrec cleared, with the oscstopenb bit cleared. 15.4.3 sim counter and reset states external reset has no effect on the sim counter. (see 15.6.2 stop mode for details.) the sim counter is free-running after all reset states. (see 15.3.2 active resets from internal sources for counter control and internal reset recovery sequences.)
system integration module (sim) mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 168 freescale semiconductor 15.5 exception control normal, sequential program execution can be changed in three different ways: interrupts: ? maskable hardware cpu interrupts ? non-maskable software interrupt instruction (swi) reset break interrupts 15.5.1 interrupts at the beginning of an interrupt, the cpu saves the cpu register contents on the stack and sets the interrupt mask (i bit) to prevent additional interrupts. at the end of an interrupt, the rti instruction recovers the cpu register contents from the stack so that normal processing can resume. figure 15-8 shows interrupt entry timing. figure 15-9 shows interrupt recovery timing. interrupts are latched, and arbitration is performed in the sim at the start of interrupt processing. the arbitration result is a constant that the cpu uses to determine which vector to fetch. once an interrupt is latched by the sim, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced (or the i bit is cleared). (see figure 15-10 .) figure 15-8 . interrupt entry timing figure 15-9. interrupt recovery timing module idb r/w interrupt dummy sp sp ? 1 sp ? 2 sp ? 3 sp ? 4 vect h vect l start addr iab dummy pc ? 1[7:0] pc ? 1[15:8] x a ccr v data h v data l opcode i bit module idb r/w interrupt sp ? 4 sp ? 3 sp ? 2 sp ? 1 sp pc pc + 1 iab ccr a x pc ? 1 [15:8] pc ? 1 [7:0] opcode operand i bit
exception control mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 169 figure 15-10. interrupt processing 15.5.1.1 hardware interrupts a hardware interrupt does not stop the current instruction. processing of a hardware interrupt begins after completion of the current instruction. when the current instruction is complete, the sim checks all pending hardware interrupts. if interrupts are not masked (i bit clear in the condition code register) and if the corresponding interrupt enable bit is set, the sim proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. no no yes no no yes no yes as many interrupts i bit set? from reset break i bit set? irq interrupt? swi instruction? rti instruction? fetch next instruction unstack cpu registers stack cpu registers set i bit load pc with interrupt vector execute instruction yes yes as exist on chip interrupt?
system integration module (sim) mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 170 freescale semiconductor if more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is serviced first. figure 15-11 demonstrates what happens when two interrupts are pending. if an interrupt is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the lda instruction is executed. figure 15-11 . interrupt recognition example the lda opcode is prefetched by both the int1 and int2 rti instructions. however, in the case of the int1 rti prefetch, this is a redundant operation. note to maintain compatibility with the m6805 family, the h register is not pushed on the stack during interrupt entry. if the interrupt service routine modifies the h register or uses the indexed addressing mode, software should save the h register and then restore it prior to exiting the routine. 15.5.1.2 swi instruction the swi instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (i bit) in the condition code register. note a software interrupt pushes pc onto the stack. a software interrupt does not push pc ? 1, as a hardware interrupt does. 15.5.1.3 interrupt status registers the flags in the interrupt status registers identify maskable interrupt sources. table 15-3 summarizes the interrupt sources and the interrupt status register flags that they set. the interrupt status registers can be useful for debugging. cli lda int1 pulh rti int2 background #$ff pshh int1 interrupt service routine pulh rti pshh int2 interrupt service routine routine
exception control mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 171 interrupt status register 1 if6?if1 ? interrupt flags 1?6 these flags indicate the presence of interrupt requests from the sources shown in table 15-3 . 1 = interrupt request present 0 = no interrupt request present bit 0 and bit 1 ? always read 0 table 15-3. interrupt sources priority interrupt source interrupt status register flag highest reset ? swi instruction ? irq pin if1 pll if2 tim1 channel 0 if3 tim1 channel 1 if4 tim1 overflow if5 tim2 channel 0 if6 tim2 channel 1 if7 tim2 overflow if8 spi receiver full if9 spi transmitter empty if10 sci receive error if11 sci receive if12 sci transmit if13 keyboard if14 adc conversion complete if15 lowest timebase module if16 address: $fe04 bit 7654321bit 0 read: if6 if5 if4 if3 if2 if1 0 0 write:rrrrrrrr reset:00000000 r= reserved figure 15-12. interrupt status register 1 (int1)
system integration module (sim) mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 172 freescale semiconductor interrupt status register 2 if14?if7 ? interrupt flags 14?7 these flags indicate the presence of interrupt requests from the sources shown in table 15-3 . 1 = interrupt request present 0 = no interrupt request present interrupt status register 3 bits 7?2 ? always read 0 if16?if15 ? interrupt flags 16?15 these flags indicate the presence of an interrupt request from the source shown in table 15-3 . 1 = interrupt request present 0 = no interrupt request present 15.5.2 reset all reset sources always have equal and highest priority and cannot be arbitrated. 15.5.3 break interrupts the break module can stop normal program flow at a software-programmable break point by asserting its break interrupt output. (see chapter 18 timer interface modules (tim1 and tim2) .) the sim puts the cpu into the break state by forcing it to the swi vector location. refer to the break interrupt subsection of each module to see how each module is affected by the break state. 15.5.4 status flag pr otection in break mode the sim controls whether status flags contained in other modules can be cleared during break mode. the user can select whether flags are protected from bei ng cleared by properly initializing the break clear flag enable bit (bcfe) in the sim break flag control register (sbfcr). address: $fe05 bit 7654321bit 0 read: if14 if13 if12 if11 if10 if9 if8 if7 write:rrrrrrrr reset:00000000 r= reserved figure 15-13. interrupt status register 2 (int2) address: $fe06 bit 7654321bit 0 read:000000if16if15 write:rrrrrrrr reset:00000000 r= reserved figure 15-14. interrupt status register 3 (int3)
low-power modes mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 173 protecting flags in break mode ensures that set fl ags will not be cleared while in break mode. this protection allows registers to be freely read and writ ten during break mode without losing status flag information. setting the bcfe bit enables the clearing mechani sms. once cleared in break mode, a flag remains cleared even when break mode is exited. status fl ags with a 2-step clearing mechanism ? for example, a read of one register followed by the read or write of another ? are protected, even when the first step is accomplished prior to entering break mode. upon leaving break mode, execution of the second step will clear the flag as normal. 15.6 low-power modes executing the wait or stop instruction puts the mcu in a low power-consumption mode for standby situations. the sim holds the cpu in a non-clocked st ate. the operation of each of these modes is described in the following subsections. both stop and wait clear the interrupt mask (i) in the condition code register, allowing interrupts to occur. 15.6.1 wait mode in wait mode, the cpu clocks are inactive while the peripheral clocks continue to run. figure 15-15 shows the timing for wait mode entry. a module that is active during wait mode can wake up the cpu with an interrupt if the interrupt is enabled. stacking for the interrupt begins one cycle after the wa it instruction during which the interrupt occurred. in wait mode, the cpu clocks are inactive. refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. some modules can be programmed to be active in wait mode. wait mode also can be exited by a reset or break. a break interrupt during wait mode sets the sim break stop/wait bit, sbsw, in the sim break status register (sbsr). if the cop disable bit, copd, in the mask option register is 0, then the computer operating properly module (cop) is enabled and remains active in wait mode. figure 15-15. wait mode entry timing wait addr + 1 same same iab idb previous data next opcode same wait addr same r/w note: previous data can be operand data or the wait opcode, depending on the last instruction.
system integration module (sim) mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 174 freescale semiconductor figure 15-16 and figure 15-17 show the timing for wait recovery. figure 15-16. wait recovery from interrupt or break figure 15-17. wait recovery from internal reset 15.6.2 stop mode in stop mode, the sim counter is reset and the system clocks are disabled. an interrupt request from a module can cause an exit from stop mode. stacking for interrupts begins after the selected stop recovery time has elapsed. reset or break also causes an exit from stop mode. the sim disables the clock generator module outputs (cgmout and cgmxclk) in stop mode, stopping the cpu and peripherals. stop recovery time is selectable using the ssrec bit in the mask option register (mor). if ssrec is set, stop recovery is reduce d from the normal delay of 4096 cgmxclk cycles down to 32. this is ideal for applications using canned os cillators that do not require long startup times from stop mode. note external crystal applications should use the full stop recovery time by clearing the ssrec bit unless the oscstopenb bit is set in mor2. the sim counter is held in reset from the execution of the stop instruction until the beginning of stop recovery. it is then used to time the recovery period. figure 15-18 shows stop mode entry timing. note to minimize stop current, all pins conf igured as inputs should be driven to a 1 or 0. $6e0c $6e0b $00ff $00fe $00fd $00fc $a6 $a6 $01 $0b $6e $a6 iab idb exitstopwait note: exitsto pwait = rst pin, cpu interrupt, or break interrupt iab idb rst $a6 $a6 $6e0b rst vct h rst vct l $a6 cgmxclk 32 cycles 32 cycles
sim registers mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 175 figure 15-18. stop mode entry timing figure 15-19. stop mode recovery from interrupt 15.7 sim registers the sim has three memory-mapped registers. table 15-4 shows the mapping of these registers. 15.7.1 sim break st atus register the sim break status register (sbsr) contains a flag to indicate that a break caused an exit from wait mode. this register is only used in emulation mode. table 15-4. sim registers address register access mode $fe00 sbsr user $fe01 srsr user $fe03 sbfcr user address: $fe00 bit 7654321bit 0 read: rrrrrr sbsw r write: note reset: 0 r= reserved note: writing a 0 clears sbsw. figure 15-20. sim break status register (sbsr) stop addr + 1 same same iab idb previous data next opcode same stop addr same r/w cpustop note : previous data can be operand data or the stop opcode, depending on the last instruction. cgmxclk int/break iab stop + 2 stop + 2 sp sp ? 1 sp ? 2 sp ? 3 stop +1 stop recovery period
system integration module (sim) mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 176 freescale semiconductor sbsw ? sim break stop/wait 1 = wait mode was exited by break interrupt. 0 = wait mode was not exited by break interrupt. sbsw can be read within the break state swi routine. the user can modify t he return address on the stack by subtracting one from it. 15.7.2 sim reset status register this register contains six flags that show the source of the last reset provided all previous reset status bits have been cleared. clear the sim reset status register by reading it. a power-on reset sets the por bit and clears all other bits in the register. por ? power-on reset bit 1 = last reset caused by por circuit 0 = read of srsr pin ? external reset bit 1 = last reset caused by external reset pin (rst ) 0 = por or read of srsr cop ? computer operating properly reset bit 1 = last reset caused by cop counter 0 = por or read of srsr ilop ? illegal opcode reset bit 1 = last reset caused by an illegal opcode 0 = por or read of srsr ilad ? illegal address reset bit (opcode fetches only) 1 = last reset caused by an opcode fetch from an illegal address 0 = por or read of srsr lvi ? low-voltage inhibit reset bit 1 = last reset caused by the lvi circuit 0 = por or read of srsr address: $fe01 bit 7654321bit 0 read: por pin cop ilop ilad 0 lvi 0 write: reset:10000000 = unimplemented figure 15-21. sim reset status register (srsr)
sim registers mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 177 15.7.3 sim break flag control register the sim break control register contains a bit that e nables software to clear status bits while the mcu is in a break state. bcfe ? break clear flag enable bit this read/write bit enables software to clear status bi ts by accessing status r egisters while the mcu is in a break state. to clear status bits duri ng the break state, the bcfe bit must be set. 1 = status bits cl earable during break 0 = status bits not clearable during break address: $fe03 bit 7654321bit 0 read: bcferrrrrrr write: reset: 0 r= reserved figure 15-22. sim break flag control register (sbfcr)
system integration module (sim) mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 178 freescale semiconductor
mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 179 chapter 16 serial peripheral interface (spi) module 16.1 introduction this section describes the serial peripheral interfac e (spi) module, which allows full-duplex, synchronous, serial communications with peripheral devices. the text that follows describes t he spi. the spi i/o pin names are ss (slave select), spsck (spi serial clock), mosi (master out slave in), and miso (master in/s lave out). the spi shares four i/o pins with four parallel i/o ports. 16.2 features features of the spi module include: full-duplex operation master and slave modes double-buffered operation with separate transmit and receive registers four master mode frequencies (maximum = bus frequency 2) maximum slave mode frequency = bus frequency serial clock with programmable polarity and phase two separately enabled interrupts: ? sprf (spi receiver full) ? spte (spi transmitter empty) mode fault error flag with cpu interrupt capability overflow error flag with cpu interrupt capability programmable wired-or mode i/o (input/output) port bit(s) software configurabl e with pullup device(s) if configured as input port bit(s) 16.3 functional description the spi module allows full-dupl ex, synchronous, serial communica tion between the mcu and peripheral devices, including other mcus. software can poll the spi status flags or spi operation can be interrupt driven. if a port bit is configured for input, then an inter nal pullup device may be enabled for that port bit. the following paragraphs describe the ope ration of the spi module. refer to figure 16-3 for a summary of the spi i/o registers.
serial peripheral in terface (spi) module mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 180 freescale semiconductor figure 16-1. block diagram highlighting spi block and pins single breakpoint break module clock generator module system integration module programmable timebase module monitor module serial peripheral 2-channel timer interface module 2 dual voltage low-voltage inhibit module 8-bit keyboard arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers user rom user ram monitor rom user rom vector space single external interrupt module porta ddra ddrc portc ddrd portd ddre porte internal bus osc1 osc2 cgmxfc rst (3) irq (3) interface module interrupt module computer operating properly module pta7/kbd7 ? ptb7/ad7 ptb6/ad6 ptb5/ad5 ptb4/ad4 ptb3/ad3 ptb2/ad2 ptb1/ad1 ptb0/ad0 v ddad /v refh 8-bit analog-to-digital converter module ptc6 (1) ptc5 (1) ptc4 (1, 2) ptc3 (1, 2) ptc2 (1, 2) ptc1 (1, 2) ptc0 (1, 2) ptd7/t2ch1 (1) ptd6/t2ch0 (1) ptd5/t1ch1 (1) ptd4/t1ch0 (1) ptd3/spsck (1) ptd2/mosi (1) ptd1/miso (1) ptd0/ss (1) pte1/rxd pte0/txd v ssad /v refl 2-channel timer interface module 1 32-khz oscillator phase-locked loop serial communications interface module power-on reset module memory map module mask option register 1 module security module mask option register 2 module power v ss v dd v ssa v dda 1. ports are software configurable with pullup device if input port. 2. higher current drive port pins 3. pin contains int egrated pullup device ddrb portb 64 bytes pta0/kbd0 (1) mc68hc08gp32a ? 32,256 bytes 512 bytes 307 bytes 36 bytes mc68hc08gp16a ? 15,872 bytes
functional description mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 181 figure 16-2. spi module block diagram addr.register name bit 7654321bit 0 $0010 spi control register (spcr) see page 195. read: sprie r spmstr cpol cpha spwom spe sptie write: reset:00101000 $0011 spi status and control reg- ister (spscr) see page 196. read: sprf errie ovrf modf spte modfen spr1 spr0 write: reset:00001000 $0012 spi data register (spdr) see page 198. read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset r = reserved = unimplemented figure 16-3. spi i/o register summary transmitter cpu interrupt request receiver/error cpu interrupt request 76543210 spr1 spmstr transmit data register shift register spr0 busclk clock select 2 clock divider 8 32 128 clock logic cpha cpol spi sprie spe spwom sprf spte ovrf m s pin control logic receive data register sptie spe internal bus modfen errie control modf spmstr mosi miso spsck ss
serial peripheral in terface (spi) module mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 182 freescale semiconductor 16.3.1 master mode the spi operates in master mode when the spi master bit, spmstr, is set. note in a multi-spi system, configure the spi modules as master or slave before enabling them. enable the master spi before enabling the slave spi. disable the slave spi before disabling the master spi. see 16.12.1 spi control register . only a master spi module can initiate transmissions. software begins the transmission from a master spi module by writing to the transmit data register. if the sh ift register is empty, the byte immediately transfers to the shift register, setting the spi transmitter empty bit, spte. the byte begins shifting out on the mosi pin under the control of the serial clock. see figure 16-4 . figure 16-4. full-duplex master-slave connections the spr1 and spr0 bits control the baud rate generator and determine the speed of the shift register. (see 16.12.2 spi status and control register .) through the spsck pin, the baud rate generator of the master also controls the shift register of the slave peripheral. as the byte shifts out on the mosi pin of the master, another byte shifts in from the slave on the master?s miso pin. the transmission ends when the receiver full bit, sprf, becomes set. at the same time that sprf becomes set, the byte from the slave transfers to the receive data register. in normal operation, sprf signals the end of a transmission. software clears sprf by reading the spi status and control register with sprf set and then reading the spi data register. writing to the spi data register (spdr) clears spte. 16.3.2 slave mode the spi operates in slave mode when spmstr is clear . in slave mode, the spsck pin is the input for the serial clock from the master mcu. before a data transmission occurs, the ss pin of the slave spi must be low. ss must remain low until the transmission is complete. see 16.6.2 mode fault error . in a slave spi module, data enters the shift register und er the control of the serial clock from the master spi module. after a byte enters the shift register of a slave spi, it transfers to the receive data register, and the sprf bit is set. to prevent an overflow condit ion, slave software then must read the receive data register before another full byte enters the shift register. shift register shift register baud rate generator master mcu slave mcu v dd mosi mosi miso miso spsck spsck ss ss
transmission formats mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 183 the maximum frequency of the spsck fo r an spi configured as a slave is the bus clock speed (which is twice as fast as the fastest master spsck clock t hat can be generated). th e frequency of the spsck for an spi configured as a slave does not have to correspond to any spi baud rate. the baud rate only controls the speed of the spsck generated by an spi configured as a master. therefore, the frequency of the spsck for an spi configured as a slave can be any frequency less than or equal to the bus speed. when the master spi starts a transmission, the data in the slave shift register begins shifting out on the miso pin. the slave can load its shift register with a new byte for the next transmission by writing to its transmit data register. the slave must write to its tr ansmit data register at l east one bus cycle before the master starts the next transmission. otherwise, the byte already in the slave shift register shifts out on the miso pin. data written to the slave shift register during a transmission remains in a buffer until the end of the transmission. when the clock phase bit (cpha) is set, the first e dge of spsck starts a transmission. when cpha is clear, the falling edge of ss starts a transmission. see 16.4 transmission formats . note spsck must be in the proper idle state before the slave is enabled to prevent spsck from appearing as a clock edge. 16.4 transmission formats during an spi transmission, data is simultaneously tr ansmitted (shifted out serially) and received (shifted in serially). a serial clock synchronizes shifting and sampling on the two serial data lines. a slave select line allows selection of an individual slave spi device; slave devices that are not selected do not interfere with spi bus activities. on a master spi device, the slave select line can optionally be used to indicate multiple-master bus contention. 16.4.1 clock phase and polarity controls software can select any of four combinations of se rial clock (spsck) phase a nd polarity using two bits in the spi control register (spcr). the clock polarity is specified by the cpol control bit, which selects an active high or low clock and has no signi ficant effect on the transmission format. the clock phase (cpha) control bit selects one of tw o fundamentally different transmission formats. the clock phase and polarity should be identical for the master spi device and the communicating slave device. in some cases, the phase and polarity are changed between transmissions to allow a master device to communicate with periphera l slaves having different requirements. note before writing to the cpol bit or the cpha bit, disable the spi by clearing the spi enable bit (spe). 16.4.2 transmission format when cpha = 0 figure 16-5 shows an spi transmission in which cpha = 0. the figure should not be used as a replacement for data sheet parametric information. two waveforms are shown for spsck: one for cpol = 0 and another for cpol = 1. the diagram may be interpreted as a master or slav e timing diagram since the serial clock (spsck), master in/slave out (miso), and master out/slave in (mosi) pins are di rectly connected between the master and the slave. the miso signal is the output from the slave, and the mosi signal is the output from the master. the ss line is the slave select input to the slave. the slave spi drives its miso output only when its slave select
serial peripheral in terface (spi) module mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 184 freescale semiconductor input (ss ) is low, so that only the selected slave drives to the master. the ss pin of the master is not shown but is assumed to be inactive. the ss pin of the master must be high or must be reconfigured as general-purpose i/o not affecting the spi. (see 16.6.2 mode fault error .) when cpha = 0, the first spsck edge is the msb capture strobe. therefore, the slave must begin driving its data before the first spsck edge, and a falling edge on the ss pin is used to start the slave data transmission. the slave?s ss pin must be toggled back to high and then low again between each byte tr ansmitted as shown in figure 16-6 . when cpha = 0 for a slave, the falling edge of ss indicates the beginning of the transmission. this causes the spi to leave its idle state and begin driving the miso pin with the msb of its data. once the transmission begins, no new data is allowed into the shift register from the transmit data register. therefore, the spi data register of the slave must be loaded with transmit data before the falling edge of ss . any data written after the falling edge is stored in th e transmit data register and transferred to the shift register after the current transmission. figure 16-5. transmission format (cpha = 0) figure 16-6. cpha/ss timing 16.4.3 transmission format when cpha = 1 figure 16-7 shows an spi transmission in which cpha = 1. the figure should not be used as a replacement for data sheet parametric information. two waveforms are shown for spsck: one for cpol = 0 and another for cpol = 1. the diagram may be interpreted as a master or slave timing diagram since the serial clock (spsck), master in/slave out (miso), and master out/slave in (mosi) pins are directly connected between the master and the slav e. the miso signal is the output from the slave, and the mosi signal is the output from the master. the ss line is the slave select input to the slave. the slave spi drives its miso output only when its slave select input (ss ) is low, so that only the selected slave drives to the master. the ss pin of the master is not shown but is assumed to be inactive. the ss pin of the master must be high or must be reconf igured as general-purpose i/o not affecting the spi. (see bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb 12345678 spsck cycle # for reference spsck; cpol = 0 spsck; cpol =1 mosi from master miso from slave ss ; to slave capture strobe byte 1 byte 3 miso/mosi byte 2 master ss slave ss cpha = 0 slave ss cpha = 1
transmission formats mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 185 16.6.2 mode fault error .) when cpha = 1, the master begins driving its mosi pin on the first spsck edge. therefore, the slave uses the first sps ck edge as a start transmission signal. the ss pin can remain low between transmissions. this format may be preferable in systems having only one master and only one slave driving the miso data line. figure 16-7. transmission format (cpha = 1) when cpha = 1 for a slave, the first edge of the spsck indicates the beginning of the transmission. this causes the spi to leave its idle state and begin driving the miso pin with the msb of its data. once the transmission begins, no new data is allowed into the shift register from the transmit data register. therefore, the spi data register of the slave must be loaded with transmit data before the first edge of spsck. any data written after the first edge is stored in the transmit data register and transferred to the shift register after the current transmission. 16.4.4 transmission initiation latency when the spi is configured as a master (spmstr = 1), writing to the spdr st arts a transmission. cpha has no effect on the delay to the start of the transmiss ion, but it does affect the initial state of the spsck signal. when cpha = 0, the spsck signal remains inactive for the first half of the first spsck cycle. when cpha = 1, the first spsck cycl e begins with an edge on the spsck line from its inactive to its active level. the spi clock rate (selected by spr1 :spr0) affects the delay from the write to spdr and the start of the spi transmission. (see figure 16-8 .) the internal spi clock in the master is a free-running derivative of the internal mcu clock. to conserve power, it is enabled only when both the spe and spmstr bits are set. since the spi clock is free-runni ng, it is uncertain where the write to the spdr occurs relative to the slower spsck. this uncertainty causes the variation in the initiation delay shown in figure 16-8 . this delay is no longer than a single spi bi t time. that is, the maximum delay is two mcu bus cycles for div2, eight mcu bus cycles for di v8, 32 mcu bus cycles for div32, and 128 mcu bus cycles for div128. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb 12345678 spsck cycle # for reference spsck; cpol = 0 spsck; cpol =1 mosi from master miso from slave ss ; to slave capture strobe
serial peripheral in terface (spi) module mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 186 freescale semiconductor figure 16-8. transmission start delay (master) write to spdr initiation delay bus mosi spsck cpha = 1 spsck cpha = 0 spsck cycle number msb bit 6 12 clock write to spdr earliest latest spsck = bus clock 2; earliest latest 2 possible start points spsck = bus clock 8; 8 possible start points earliest latest spsck = bus clock 32; 32 possible start points earliest latest spsck = bus clock 128; 128 possible start points write to spdr write to spdr write to spdr bus clock bit 5 3 bus clock bus clock bus clock initiation delay from write spdr to transfer begin
queuing transm ission data mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 187 16.5 queuing tr ansmission data the double-buffered transmit data register allows a data byte to be queued and transmitted. for an spi configured as a master, a queued data byte is transm itted immediately after the previous transmission has completed. the spi transmitter empty flag (spte) indicates when the transmit data buffer is ready to accept new data. write to the transmit data register only when spte is high. figure 16-9 shows the timing associated with doing back-to-back transmiss ions with the spi (spsck has cpha: cpol = 1:0). figure 16-9. sprf/spte cpu interrupt timing the transmit data buffer allows back- to-back transmissions without the sl ave precisely timing its writes between transmissions as in a system with a single data buffer. also, if no new data is written to the data buffer, the last value contained in the shift r egister is the next data word to be transmitted. for an idle master or idle slave that has no data loaded into its transmit buffer, the spte is set again no more than two bus cycles after the transmit buffer emptie s into the shift register. this allows the user to queue up a 16-bit value to send. for an already active sl ave, the load of the shift register cannot occur until the transmission is completed. this implies that a back-to-back write to the transmit data register is not possible. spte indicates when the next write can occur. bit 3 mosi spsck spte write to spdr 1 cpu writes byte 2 to spdr, queueing byte 2 cpu writes byte 1 to spdr, clearing spte bit. byte 1 transfers from transmit data 3 1 2 2 3 5 register to shift register, setting spte bit. sprf read spscr msb bit 6 bit 5 bit 4 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 byte 2 transfers from transmit data cpu writes byte 3 to spdr, queueing byte byte 3 transfers from transmit data 5 8 10 8 10 4 first incoming byte transfers from shift 6 cpu reads spscr with sprf bit set. 4 6 9 second incoming byte transfers from shift 9 11 and clearing spte bit. register to shift register, setting spte bit. register to receive data register, setting sprf bit. 3 and clearing spte bit. register to shift register, setting spte bit. register to receive data register, setting sprf bit. 12 cpu reads spdr, clearing sprf bit. bit 5 bit 4 byte 1 byte 2 byte 3 7 12 read spdr 7 cpu reads spdr, clearing sprf bit. 11 cpu reads spscr with sprf bit set. cpha:cpol = 1:0
serial peripheral in terface (spi) module mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 188 freescale semiconductor 16.6 error conditions the following flags signal spi error conditions: overflow (ovrf) ? failing to read the spi data register before the next full byte enters the shift register sets the ovrf bit. the new byte does not transfer to the receive data register, and the unread byte still can be read. ovrf is in the spi status and control register. mode fault error (modf) ? the modf bit indicates that the voltage on the slave select pin (ss ) is inconsistent with the mode of the spi. modf is in the spi status and control register. 16.6.1 overflow error the overflow flag (ovrf) becomes set if the receive data register still has unread data from a previous transmission when the capture strobe of bit 1 of th e next transmission occurs. the bit 1 capture strobe occurs in the middle of spsck cycle 7 (see figure 16-5 and figure 16-7 .) if an overflow occurs, all data received after the overflow and before the ovrf bit is cleared does not transfer to the receive data register and does not set the spi receiver full bit (sprf). the unread data that transferred to the receive data register before the overflow occurred can still be read. therefore, an overflow error always indicates the loss of data. clear the overflow flag by reading the spi status and control register and then reading the spi data register. ovrf generates a receiver/error cpu interrupt request if the error interrupt enable bit (errie) is also set. the sprf, modf, and ovrf interrupts share the same cpu interrupt vector (see figure 16-12 .) it is not possible to enable modf or ovrf individually to generate a receiver/error cpu interrupt request. however, leaving modfen low prevents modf from being set. if the cpu sprf interrupt is enabled and the ovrf in terrupt is not, watch for an overflow condition. figure 16-10 shows how it is possible to miss an overflow. the first part of figure 16-10 shows how it is possible to read the spscr and spdr to clear the sprf without problems. however, as illustrated by the second transmission example, the ovrf bit c an be set in between the time that spscr and spdr are read. in this case, an overflow can be missed easily. since no more sprf interrupts can be generated until this ovrf is serviced, it is not obvious that bytes are being lost as more transmissions are completed. to prevent this, either enable the ovrf interrupt or do another read of the spscr following the read of the spdr. this ensures that the ovrf was not set before the sprf was cleared and that future transmissions can set the sprf bit. figure 16-11 illustrates this process. g enerally, to avoid this second spscr read, enable the ovrf to the cpu by setting the errie bit.
error conditions mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 189 figure 16-10. missed read of overflow condition figure 16-11. clearing sprf when ovrf interrupt is not enabled read read ovrf sprf byte 1 byte 2 byte 3 byte 4 byte 1 sets sprf bit. cpu reads spscr with sprf bit set cpu reads byte 1 in spdr, byte 2 sets sprf bit. cpu reads spscr with sprf bit set byte 3 sets ovrf bit. byte 3 is lost. cpu reads byte 2 in spdr, clearing sprf bit, byte 4 fails to set sprf bit because 1 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 clearing sprf bit. but not ovrf bit. ovrf bit is not cleared. byte 4 is lost. and ovrf bit clear. and ovrf bit clear. spscr spdr read read ovrf sprf byte 1 byte 2 byte 3 byte 4 1 byte 1 sets sprf bit. cpu reads spscr with sprf bit set cpu reads byte 1 in spdr, cpu reads spscr again byte 2 sets sprf bit. cpu reads spscr with sprf bit set byte 3 sets ovrf bit. byte 3 is lost. cpu reads byte 2 in spdr, cpu reads spscr again cpu reads byte 2 spdr, byte 4 sets sprf bit. cpu reads spscr. cpu reads byte 4 in spdr, cpu reads spscr again 1 2 3 clearing sprf bit. 4 to check ovrf bit. 5 6 7 8 9 clearing sprf bit. to check ovrf bit. 10 clearing ovrf bit. 11 12 13 14 2 3 4 5 6 7 8 9 10 11 12 13 14 clearing sprf bit. to check ovrf bit. spi receive complete and ovrf bit clear. and ovrf bit clear. spscr spdr
serial peripheral in terface (spi) module mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 190 freescale semiconductor 16.6.2 mode fault error setting spmstr selects master mode and configures the spsck and mosi pins as outputs and the miso pin as an input. clearing spmstr selects sl ave mode and configures the spsck and mosi pins as inputs and the miso pin as an output. the mode fault bit, modf, becomes set any time the state of the slave select pin, ss , is inconsistent with the mode selected by spmstr. to prevent spi pin contention and damage to the mcu, a mode fault error occurs if: the ss pin of a slave spi goes high during a transmission the ss pin of a master spi goes low at any time for the modf flag to be set, the mode fault error enable bit (modfen) must be set. clearing the modfen bit does not clear the modf flag but does prevent modf from being set again after modf is cleared. modf generates a receiver/error cpu interrupt request if the error interrupt enable bit (errie) is also set. the sprf, modf, and ovrf interrupts share the same cpu interrupt vector. (see figure 16-12 .) it is not possible to enable modf or ovrf individual ly to generate a receiver/error cpu interrupt request. however, leaving modfen low prevents modf from being set. in a master spi with the mode fault enable bit (modfe n) set, the mode fault flag (modf) is set if ss goes low. a mode fault in a master spi causes the following events to occur: if errie = 1, the spi generates an spi receiver/error cpu interrupt request. the spe bit is cleared. the spte bit is set. the spi state counter is cleared. the data direction register of the shared i/o port regains control of port drivers. note to prevent bus contention with another master spi after a mode fault error, clear all spi bits of the data direction register of the shared i/o port before enabling the spi. when configured as a slave (spmstr = 0), the modf flag is set if ss goes high during a transmission. when cpha = 0, a transmission begins when ss goes low and ends once the incoming spsck goes back to its idle level following the shift of the eighth data bit. when cpha = 1, the transmission begins when the spsck leaves its idle level and ss is already low. the transmi ssion continues until the spsck returns to its idle level following the shift of the last data bit. see 16.4 transmission formats . note setting the modf flag does not clear the spmstr bit. spmstr has no function when spe = 0. reading spmstr when modf = 1 shows the difference between a modf occurring when the spi is a master and when it is a slave. when cpha = 0, a modf occurs if a slave is selected (ss is low) and later unselected (ss is high) even if no spsck is sent to that slave. this happens because ss low indicates the start of the transmission (miso driven out with the value of msb) for cpha = 0. when cpha = 1, a slave can be selected and then later unselected with no transmission occurring. therefore, modf does not occur since a transmission was never begun.
interrupts mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 191 in a slave spi (mstr = 0), modf generates an spi re ceiver/error cpu interrupt request if the errie bit is set. the modf bit does not clear the spe bit or re set the spi in any way. software can abort the spi transmission by clearing the spe bit of the slave. note a high on the ss pin of a slave spi puts the miso pin in a high impedance state. also, the slave spi ignores all incoming spsck clocks, even if it was already in the middle of a transmission. to clear the modf flag, read the spscr with the modf bit set and then write to the spcr register. this entire clearing mechanism must occur with no modf condition existing or else the flag is not cleared. 16.7 interrupts four spi status flags can be enabled to generate cpu interrupt requests. see table 16-1 . reading the spi status and control register with sprf set and then reading the receive data register clears sprf. the clearing mechanism for the spte flag is always just a write to the transmit data register. the spi transmitter interrupt enable bit (sptie) enables the spte flag to generate transmitter cpu interrupt requests, provided that the spi is enabled (spe = 1). the spi receiver interrupt enable bit (sprie) enables sprf to generate receiver cpu interrupt requests, regardless of the state of spe. see figure 16-12 . figure 16-12. spi interrupt request generation table 16-1. spi interrupts flag request spte ? transmitter empty spi transmitter cpu interrupt request (sptie = 1, spe = 1) sprf ? receiver full spi receiver cpu interrupt request (sprie = 1) ovrf ? overflow spi receiver/e rror interrupt request (errie = 1) modf ? mode fault spi receiver/error interrupt request (errie = 1) spte sptie sprf sprie spe cpu interrupt request cpu interrupt request spi transmitter spi receiver/error errie modf ovrf
serial peripheral in terface (spi) module mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 192 freescale semiconductor the error interrupt enable bit (errie) enables both the modf and ovrf bits to generate a receiver/error cpu interrupt request. the mode fault enable bit (modfen) can prevent the modf flag from being set so that only the ovrf bit is enabled by the errie bit to generate receiver/error cpu interrupt requests. the following sources in the spi status and control register can generate cpu interrupt requests: spi receiver full bit (sprf) ? sprf becomes set ever y time a byte transfers from the shift register to the receive data register. if the spi receiver interrupt enable bit, sprie, is also set, sprf generates an spi receiver/error cpu interrupt request. spi transmitter empty (spte) ? spte becomes set every time a byte transfers from the transmit data register to the shift register. if the spi transmit interrupt enable bit, sptie, is also set, spte generates an spte cpu interrupt request. 16.8 resetting the spi any system reset completely resets the spi. partial resets occur whenever the spi enable bit (spe) is 0. whenever spe is 0, the following occurs: the spte flag is set. any transmission currently in progress is aborted. the shift register is cleared. the spi state counter is cleared, making it ready for a new complete transmission. all the spi port logic is defaul ted back to being general-purpose i/o. these items are reset only by a system reset: all control bits in the spcr register all control bits in the spscr regist er (modfen, errie, spr1, and spr0) the status flags sprf, ovrf, and modf by not resetting the control bits when spe is low, the user can clear spe betw een transmissions without having to set all control bits again when spe is set back high for t he next transmission. by not resetting the sprf, ovrf, and modf flags, the user can still service these interrupts after the spi has been disabled. the user can disable the spi by writing 0 to the spe bit. the spi can also be disabled by a mode fault occurring in an spi that wa s configured as a master with the modfen bit set. 16.9 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 16.9.1 wait mode the spi module remains active after the execution of a wait instruction. in wait mode the spi module registers are not accessible by the cpu. any enabled cpu interrupt request from the spi module can bring the mcu out of wait mode. if spi module functions are not required during wait mode, reduce power consumption by disabling the spi module before executing the wait instruction.
spi during break interrupts mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 193 to exit wait mode when an overflow condition occu rs, enable the ovrf bit to generate cpu interrupt requests by setting the error interrupt enable bit (errie). see 16.7 interrupts . 16.9.2 stop mode the spi module is inactive after the execution of a stop instruction. the stop instruction does not affect register conditions. spi operation resumes after an external interrupt. if stop mode is exited by reset, any transfer in progress is aborted, and the spi is reset. 16.10 spi during break interrupts the system integration module (sim) controls whether status bits in other modules can be cleared during the break state. bcfe in the sim break flag control r egister (sbfcr) enables software to clear status bits during the break state. see chapter 15 system integration module (sim). to allow software to clear status bits during a break interrupt, write a 1 to bcfe. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break state, write a 0 to bcfe. with bcfe at 0 (its default state), software can read and write i/o registers during the break state wi thout affecting status bits. some status bits have a 2-step read/write clearing procedure. if software does the first step on such a bit before the break, the bit cannot change during the break state as long as bc fe is 0. after the break, doing the second step clears the status bit. since the spte bit cannot be cleared during a break wi th bcfe cleared, a write to the transmit data register in break mode does not initiate a transmission nor is this data transferred into the shift register. therefore, a write to the spdr in break mode with bcfe cleared has no effect. 16.11 i/o signals the spi module has four i/o pins: miso ? master input/slave output mosi ? master output/slave input spsck ? serial clock ss ? slave select 16.11.1 miso (mas ter in/slave out) miso is one of the two spi module pins that transmits se rial data. in full duplex operation, the miso pin of the master spi module is connected to the miso pin of the slave spi module. the master spi simultaneously receives data on its miso pin and transmits data from its mosi pin. slave output data on the miso pin is enabled only w hen the spi is configured as a slave. the spi is configured as a slave when its spmstr bit is 0 and its ss pin is low. to support a multiple-slave system, a high on the ss pin puts the miso pin in a high-impedance state. when enabled, the spi controls data direction of the mi so pin regardless of the st ate of the data direction register of the shared i/o port.
serial peripheral in terface (spi) module mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 194 freescale semiconductor 16.11.2 mosi (master out/slave in) mosi is one of the two spi module pins that transmits serial data. in full-duplex operation, the mosi pin of the master spi module is connected to the mosi pin of the slave spi module. the master spi simultaneously transmits data from its mosi pin and receives data on its miso pin. when enabled, the spi controls data direction of the mo si pin regardless of the st ate of the data direction register of the shared i/o port. 16.11.3 spsck (serial clock) the serial clock synchronizes data transmission between master and sl ave devices. in a master mcu, the spsck pin is the clock output. in a slave mcu, the spsck pin is the cl ock input. in full-duplex operation, the master and slave mcus exchange a byte of data in eight serial clock cycles. when enabled, the spi contro ls data direction of the spsck pin regardless of the state of the data direction register of the shared i/o port. 16.11.4 ss (slave select) the ss pin has various functions depending on the current state of the spi. for an spi configured as a slave, the ss is used to select a slave. for cpha = 0, the ss is used to define the start of a transmission. (see 16.4 transmission formats .) since it is used to indicate the start of a transmission, ss must be toggled high and low between each byte transmitted for the cpha = 0 format. however, it can remain low between transmissions for the cpha = 1 format. see figure 16-13 . when an spi is configured as a slave, the ss pin is always configured as an input. it cannot be used as a general-purpose i/o regardless of the state of the modfen control bit. however, the modfen bit can still prevent the state of ss from creating a modf error. see 16.12.2 spi status and control register. figure 16-13. cpha/ss timing note a high on the ss pin of a slave spi puts the miso pin in a high-impedance state. the slave spi ignores all inco ming spsck clocks, even if it was already in the middle of a transmission. when an spi is configured as a master, the ss input can be used in conjunc tion with the modf flag to prevent multiple masters from driving mosi and spsck. (see 16.6.2 mode fault error.) for the state of the ss pin to set the modf flag, the modfen bit in t he spsck register must be set. if modfen is 0 for an spi master, the ss pin can be used as a general-purpose i/o under the control of the data direction register of the shared i/o port. when modfen is 1, ss is an input-only pin to the spi regardless of the state of the data direction register of the shared i/o port. the cpu can always read the state of the ss pin by configuring the appropriate pin as an input and reading the port data register. see table 16-2. byte 1 byte 3 miso/mosi byte 2 master ss slave ss cpha = 0 slave ss cpha = 1
i/o registers mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 195 16.12 i/o registers three registers control and monitor spi operation: spi control register (spcr) spi status and control register (spscr) spi data register (spdr) 16.12.1 spi control register the spi control register: enables spi module interrupt requests configures the spi module as master or slave selects serial clock polarity and phase configures the spsck, mosi, and miso pins as open-drain outputs enables the spi module sprie ? spi receiver interrupt enable bit this read/write bit enables cpu interrupt requests generated by the sprf bit. the sprf bit is set when a byte transfers from the sh ift register to the receive data register. reset clears the sprie bit. 1 = sprf cpu interrupt requests enabled 0 = sprf cpu interrupt requests disabled spmstr ? spi master bit this read/write bit selects master mode operation or slave mode operation. reset sets the spmstr bit. 1 = master mode 0 = slave mode table 16-2. spi configuration spe spmstr modfen spi configuration function of ss pin 0 x (1)) 1. x = don?t care x not enabled general-purpose i/o; ss ignored by spi 1 0 x slave input-only to spi 1 1 0 master without modf general-purpose i/o; ss ignored by spi 1 1 1 master with modf input-only to spi address: $0010 bit 7654321bit 0 read: sprie r spmstr cpol cpha spwom spe sptie write: reset:00101000 r = reserved figure 16-14. spi control register (spcr)
serial peripheral in terface (spi) module mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 196 freescale semiconductor cpol ? clock polarity bit this read/write bit determines the logic stat e of the spsck pin betw een transmissions. (see figure 16-5 and figure 16-7 .) to transmit data between spi modules, the spi modules must have identical cpol values. reset cl ears the cpol bit. cpha ? clock phase bit this read/write bit controls the timing relati onship between the serial clock and spi data. (see figure 16-5 and figure 16-7 .) to transmit data between spi modules, the spi modules must have identical cpha values. when cpha = 0, the ss pin of the slave spi module must be high between bytes. (see figure 16-13 .) reset sets the cpha bit. spwom ? spi wired-or mode bit this read/write bit disables the pullup devices on pins spsck, mos i, and miso so that those pins become open-drain outputs. 1 = wired-or spsck, mosi, and miso pins 0 = normal push-pull spsc k, mosi, and miso pins spe ? spi enable this read/write bit enables the spi module. cleari ng spe causes a partial reset of the spi. (see 16.8 resetting the spi .) reset clears the spe bit. 1 = spi module enabled 0 = spi module disabled sptie? spi transmit interrupt enable this read/write bit enables cpu interrupt requests generated by the spte bit. spte is set when a byte transfers from the transmit data register to the shift register. reset clears the sptie bit. 1 = spte cpu interrupt requests enabled 0 = spte cpu interrupt requests disabled 16.12.2 spi status and control register the spi status and control register c ontains flags to si gnal these conditions: receive data register full failure to clear sprf bit before next byte is received (overflow error) inconsistent logic level on ss pin (mode fault error) transmit data register empty the spi status and control register also c ontains bits that perform these functions: enable error interrupts enable mode fault error detection select master spi baud rate address: $0011 bit 7654321bit 0 read: sprf errie ovrf modf spte modfen spr1 spr0 write: reset:00001000 = unimplemented figure 16-15. spi status and control register (spscr)
i/o registers mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 197 sprf ? spi receiver full bit this clearable, read-only flag is set each time a byte tr ansfers from the shift register to the receive data register. sprf generates a cpu interrupt request if the sprie bit in the spi control register is set also. during an sprf cpu interrupt, the cpu clears sprf by reading the spi status and control register with sprf set and then reading the spi data register. reset clears the sprf bit. 1 = receive data register full 0 = receive data register not full errie ? error interrupt enable bit this read/write bit enables the modf and ovrf bits to generate cpu interrupt requests. reset clears the errie bit. 1 = modf and ovrf can generate cpu interrupt requests 0 = modf and ovrf cannot generate cpu interrupt requests ovrf ? overflow bit this clearable, read-only flag is set if software does not read the byte in the receive data register before the next full byte enters the shift register. in an ov erflow condition, the byte already in the receive data register is unaffected, and the byte that shifted in last is lost. clear the ovrf bit by reading the spi status and control register with ovrf set and then reading the receive data register. reset clears the ovrf bit. 1 = overflow 0 = no overflow modf ? mode fault bit this clearable, read-only flag is set in a slave spi if the ss pin goes high during a transmission with modfen set. in a master spi, the modf flag is set if the ss pin goes low at any time with the modfen bit set. clear modf by reading the spi stat us and control register (spscr) with modf set and then writing to the spi control regi ster (spcr). reset clears the modf bit. 1 = ss pin at inappropriate logic level 0 = ss pin at appropriate logic level spte ? spi transmitter empty bit this clearable, read-only flag is set each time the transmit data register transfers a byte into the shift register. spte generates an spte cpu interrupt request if sptie in the spi control register is set also. note do not write to the spi data register unless spte is high. during an spte cpu interrupt, the cpu clears spt e by writing to the transmit data register. reset sets the spte bit. 1 = transmit data register empty 0 = transmit data register not empty modfen ? mode fault enable bit this read/write bit, when set, allows the modf flag to be set. if the modf flag is set, clearing modfen does not clear the modf flag. if the spi is enabled as a master and the modfen bit is 0, then the ss pin is available as a general-purpose i/o. if the modfen bit is 1, then the ss pin is not available as a general-purpose i/o. when the spi is enabled as a slave, the ss pin is not available as a general-pu rpose i/o regardless of the value of modfen. see 16.11.4 ss (slave select).
serial peripheral in terface (spi) module mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 198 freescale semiconductor if the modfen bit is 0, the level of the ss pin does not affect the operation of an enabled spi configured as a master. for an enabled spi configured as a slave, having modfen low only prevents the modf flag from being set. it does not affect any other part of spi operation. see 16.6.2 mode fault error. spr1 and spr0 ? spi baud rate select bits in master mode, these read/write bits select one of four baud rates as shown in table 16-3 . spr1 and spr0 have no effect in slave mode. reset clears spr1 and spr0. use this formula to calculate the spi baud rate: 16.12.3 spi data register the spi data register consists of the read-only receive data register and the write-only transmit data register. writing to the spi data register writes dat a into the transmit data register. reading the spi data register reads data from the receive data register. the transmit data and receive data registers are separate registers that can c ontain different values. see figure 16-2 . r7?r0/t7?t0 ? receive/transmit data bits note do not use read-modify-write instructio ns on the spi data register since the register read is not the same as the register written. table 16-3. spi master baud rate selection spr1 and spr0 baud rate divisor (bd) 00 2 01 8 10 32 11 128 address: $0012 bit 7654321bit 0 read:r7r6r5r4r3r2r1r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset figure 16-16. spi data register (spdr) baud rate = busclk bd
mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 199 chapter 17 timebase module (tbm) 17.1 introduction this section describes the timebase module (tbm). the tbm will generate periodic interrupts at user selectable rates using a counter cloc ked by the external clock source. this tbm version uses 15 divider stages, eight of which are user selectable. a configur ation option bit to select an additional 128 divide of the external clock source can be selected. see chapter 11 mask option registers (mor2 and mor1) 17.2 features features of the tbm module include: external clock or an additional divide-by-128 sele cted by configuration option bit as clock source software configurable periodic interrupts with di vide-by: 8, 16, 32, 64, 128, 2048, 8192, and 32768 taps of the selected clock source configurable for operation during stop m ode to allow periodic wakeup from stop 17.3 functional description this module can generate a periodic interrupt by di viding the clock source supplied from the clock generator module, cgmxclk. the counter is initialized to all 0s when tbon bit is cleared. the counter, shown in figure 17-1 , starts counting when the tbon bit is set. when the counter ov erflows at the tap selected by tbr2?tbr0, the tbif bit gets set. if the tbie bit is set, an interrupt request is sent to the cpu. the tbif flag is cleared by writing a 1 to the tack bit. the first time the tbif flag is set after enabling the timebase module, the interrupt is generated at approximately half of the ov erflow period. subsequent events occur at the exact period. the timebase module may remain active after execution of the stop instruction if the crystal oscillator has been enabled to operate during stop mode through the oscstopenb bit in the mask option register. the timebase module can be used in this mode to generate a periodic wakeup from stop mode. 17.4 interrupts the timebase module can periodically interrupt the cpu with a rate defined by the selected tbmclk and the select bits tbr2?tbr0. when the timebase counter c hain rolls over, the tbif flag is set. if the tbie bit is set, enabling the timebase interrupt, the c ounter chain overflow will generate a cpu interrupt request. note interrupts must be acknowledged by writing a 1 to the tack bit.
timebase module (tbm) mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 200 freescale semiconductor figure 17-1. timebase block diagram 2 2 2 2 2 2 2 2 2 2 2 2 2 2 sel 0 0 0 0 0 1 0 1 0 0 1 1 tbif tbr1 tbr0 tbie tbmint tbon 2 r tack tbr2 1 0 0 1 0 1 1 1 0 1 1 1 tbmclk from cgm module tbmclksel from mor2 divide by 128 prescaler 0 1 cgmxclk
tbm interrupt rate mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 201 17.5 tbm interrupt rate the interrupt rate is determined by the equation: where: f cgmxclk = frequency supplied from the clock generator (cgm) module divider = divider value as determined by tbr2?tbr0 settings and tbmclksel, see table 17-1 as an example, a clock source of 32.768 khz, with the tbmclksel set for divide-by-128 and tbr2?tbr0 set to {101}, the divider tap is 1 and the interrupt rate calculates to: 4096/32,768 = 125 ms note do not change tbr2?tbr0 bits while the timebase is enabled (tbon = 1). 17.6 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 17.6.1 wait mode the timebase module remains active after execution of the wait instruction. in wait mode the timebase register is not accessible by the cpu. if the timebase functions are not required during wa it mode, reduce the power consumption by stopping the timebase before executing the wait instruction. 17.6.2 stop mode the timebase module may remain active after execution of the stop instruction if the internal clock generator has been enabled to operate during stop mode through the oscstopenb bit in the mask option register. the timebase modul e can be used in this mode to generate a periodic wakeup from stop mode. table 17-1. timebase divider selection tbr2 tbr1 tbr0 divider tap tbmclksel 01 0 0 0 32,768 4,194,304 0 0 1 8192 1,048,576 0 1 0 2048 262144 0 1 1 128 16,384 1 0 0 64 8192 1 0 1 32 4096 1 1 0 16 2048 1 1 1 8 1024 t tbmrate = divider f cgmxclk
timebase module (tbm) mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 202 freescale semiconductor if the internal clock generator has not been enabled to operate in stop mode, the timebase module will not be active during stop mode. in stop mode, the ti mebase register is not accessible by the cpu. if the timebase functions are not required during stop mode, reduce power consumption by disabling the timebase module before execut ing the stop instruction. 17.7 timebase control register the timebase has one register, the timebase control register (tbcr), which is used to enable the timebase interrupts and set the rate. tbif ? timebase interrupt flag this read-only flag bit is set when th e timebase counter has rolled over. 1 = timebase interrupt pending 0 = timebase interrupt not pending tbr2?tbr0 ? timebase divider selection bits these read/write bits select the tap in the counter to be used for timebase interrupts as shown in table 17-1 . note do not change tbr2?tbr0 bits while the timebase is enabled (tbon = 1). tack? timebase acknowledge bit the tack bit is a write-only bit and always reads as 0. writing a 1 to this bit clears tbif, the timebase interrupt flag bit. writing a 0 to this bit has no effect. 1 = clear timebase interrupt flag 0 = no effect tbie ? timebase interrupt enabled bit this read/write bit enables the timebase interrupt when the tbif bit becomes set. reset clears the tbie bit. 1 = timebase interrupt is enabled. 0 = timebase interrupt is disabled. tbon ? timebase enabled bit this read/write bit enables the timebase. timebase may be turned off to reduce power consumption when its function is not necessary. the counter can be initialized by clearing and then setting this bit. reset clears the tbon bit. 1 = timebase is enabled. 0 = timebase is disabled and t he counter initialized to 0s. address: $001c bit 7654321bit 0 read: tbif tbr2 tbr1 tbr0 0 tbie tbon r write: tack reset:00000000 = unimplemented r = reserved figure 17-2. timebase control register (tbcr)
mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 203 chapter 18 timer interface modules (tim1 and tim2) 18.1 introduction this section describes the timer interface (tim) modul e. the tim is a two-channel timer that provides a timing reference with input capture, output compare, and pulse-width- modulation functions. figure 18-2 is a block diagram of the tim. this particular mcu has two timer interfac e modules which are denoted as tim1 and tim2. 18.2 features features of the tim include: two input capture/output compare channels: ? rising-edge, falling-edge, or any-edge input capture trigger ? set, clear, or toggle output compare action buffered and unbuffered pulse-width-modulation (pwm) signal generation programmable tim clock input with 7-frequenc y internal bus clock prescaler selection free-running or modulo up-count operation toggle any channel pin on overflow tim counter stop and reset bits 18.3 pin name conventions the text that follows describes both timers, tim1 and tim2. the tim input/output (i/o) pin names are t[1,2]ch0 (timer channel 0) and t[1,2]ch1 (timer channel 1), where ?1? is used to indicate tim1 and ?2? is used to indicate tim2. the two tims share four i/ o pins with four port d i/o port pins. the full names of the tim i/o pins are listed in table 18-1 . the generic pin names appear in the text that follows. note references to either timer 1 or timer 2 may be made in the following text by omitting the timer number. for example, tch0 may refer generically to t1ch0 and t2ch0, and tch1 ma y refer to t1ch1 and t2ch1. table 18-1. pin name conventions tim generic pin names: t[1,2]ch0 t[1,2]ch1 full tim pin names: tim1 ptd4/t1ch0 ptd5/t1ch1 tim2 ptd6/t2ch0 ptd7/t2ch1
timer interface modu les (tim1 and tim2) mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 204 freescale semiconductor figure 18-1. block diagram highlighting tim blocks and pins single breakpoint break module clock generator module system integration module programmable timebase module monitor module serial peripheral 2-channel timer interface module 2 dual voltage low-voltage inhibit module 8-bit keyboard arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers user rom user ram monitor rom user rom vector space single external interrupt module porta ddra ddrc portc ddrd portd ddre porte internal bus osc1 osc2 cgmxfc rst (3) irq (3) interface module interrupt module computer operating properly module pta7/kbd7 ? ptb7/ad7 ptb6/ad6 ptb5/ad5 ptb4/ad4 ptb3/ad3 ptb2/ad2 ptb1/ad1 ptb0/ad0 v ddad /v refh 8-bit analog-to-digital converter module ptc6 (1) ptc5 (1) ptc4 (1, 2) ptc3 (1, 2) ptc2 (1, 2) ptc1 (1, 2) ptc0 (1, 2) ptd7/t2ch1 (1) ptd6/t2ch0 (1) ptd5/t1ch1 (1) ptd4/t1ch0 (1) ptd3/spsck (1) ptd2/mosi (1) ptd1/miso (1) ptd0/ss (1) pte1/rxd pte0/txd v ssad /v refl 2-channel timer interface module 1 32-khz oscillator phase-locked loop serial communications interface module power-on reset module memory map module mask option register 1 module security module mask option register 2 module power v ss v dd v ssa v dda 1. ports are software configurable with pullup device if input port. 2. higher current drive port pins 3. pin contains int egrated pullup device ddrb portb 64 bytes pta0/kbd0 (1) mc68hc08gp32a ? 32,256 bytes 512 bytes 307 bytes 36 bytes mc68hc08gp16a ? 15,872 bytes
functional description mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 205 18.4 functional description figure 18-2 shows the structure of the tim. the central component of the tim is the 16-bit tim counter that can operate as a free-running counter or a mo dulo up-counter. the tim counter provides the timing reference for the input capture and output compare functions. the tim counter modulo registers, tmodh:tmodl, control the modulo value of the tim counter. software can read the tim counter value at any time without affecting the counting sequence. the two tim channels (per timer) are programmable independently as input capture or output compare channels. if a channel is configured as input capture, then an internal pullup device may be enabled for that channel. see 12.5.3 port d input pullup enable register. figure 18-3 summarizes the timer registers. note references to either timer 1 or timer 2 may be made in the following text by omitting the timer number. for example, tsc may generically refer to both t1sc and t2sc. figure 18-2. tim block diagram ms1a ch0f prescaler prescaler select internal 16-bit comparator ps2 ps1 ps0 16-bit comparator 16-bit latch tch0h:tch0l tof toie 16-bit comparator 16-bit latch tch1h:tch1l channel 0 channel 1 tmodh:tmodl trst tstop tov0 ch0ie tov1 ch1ie ch1max ch0max 16-bit counter internal bus bus clock t[1,2]ch0 t[1,2]ch1 interrupt logic port logic interrupt logic interrupt logic port logic els0a els0b els1a els1b ms0b ch1f ms0a
timer interface modu les (tim1 and tim2) mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 206 freescale semiconductor addr.register name bit 7654321bit 0 $0020 timer 1 status and control register (t1sc) see page 213. read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 $0021 timer 1 counter register high (t1cnth) see page 214. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $0022 timer 1 counter register low (t1cntl) see page 214. read:bit 7654321bit 0 write: reset:00000000 $0023 timer 1 counter modulo register high (t1modh) see page 215. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 $0024 timer 1 counter modulo register low (t1modl) see page 215. read: bit 7654321bit 0 write: reset:11111111 $0025 timer 1 channel 0 status and control register (t1sc0) see page 215. read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0026 timer 1 channel 0 register high (t1ch0h) see page 218. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0027 timer 1 channel 0 register low (t1ch0l) see page 218. read: bit 7654321bit 0 write: reset: indeterminate after reset $0028 timer 1 channel 1 status and control register (t1sc1) see page 218. read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 $0029 timer 1 channel 1 register high (t1ch1h) see page 218. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $002a timer 1 channel 1 register low (t1ch1l) see page 218. read: bit 7654321bit 0 write: reset: indeterminate after reset $002b timer 2 status and control register (t2sc) see page 213. read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 = unimplemented figure 18-3. tim i/o register summary (sheet 1 of 2)
functional description mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 207 18.4.1 tim counter prescaler the tim clock source can be one of the seven presca ler outputs. the prescaler generates seven clock rates from the internal bus clock. the prescaler select bits, ps[2:0], in the tim status and control register select the tim clock source. 18.4.2 input capture with the input capture function, the tim can capture the time at which an external event occurs. when an active edge occurs on the pin of an input capture chann el, the tim latches the contents of the tim counter $002c timer 2 counter register high (t2cnth) see page 214. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $002d timer 2 counter register low (t2cntl) see page 214. read:bit 7654321bit 0 write: reset:00000000 $002e timer 2 counter modulo register high (t2modh) see page 215. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 $002f timer 2 counter modulo register low (t2modl) see page 215. read: bit 7654321bit 0 write: reset:11111111 $0030 timer 2 channel 0 status and control register (t2sc0) see page 215. read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0031 timer 2 channel 0 register high (t2ch0h) see page 218. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0032 timer 2 channel 0 register low (t2ch0l) see page 218. read: bit 7654321bit 0 write: reset: indeterminate after reset $0033 timer 2 channel 1 status and control register (t2sc1) see page 215. read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 $0034 timer 2 channel 1 register high (t2ch1h) see page 218. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0035 timer 2 channel 1 register low (t2ch1l) see page 218. read: bit 7654321bit 0 write: reset: indeterminate after reset addr.register name bit 7654321bit 0 = unimplemented figure 18-3. tim i/o register summary (sheet 2 of 2)
timer interface modu les (tim1 and tim2) mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 208 freescale semiconductor into the tim channel registers, tchxh:tchxl. the polarity of the active edge is programmable. input captures can generate tim cpu interrupt requests. 18.4.3 output compare with the output compare function, the tim can generat e a periodic pulse with a programmable polarity, duration, and frequency. when the counter reaches the value in the registers of an output compare channel, the tim can set, clear, or toggle the ch annel pin. output compares can generate tim cpu interrupt requests. 18.4.3.1 unbuffered output compare any output compare channel can generate unbuffer ed output compare pulses as described in 18.4.3 output compare . the pulses are unbuffered because changing t he output compare value requires writing the new value over the old value currently in the tim channel registers. an unsynchronized write to the tim channel regist ers to change an output compare value could cause incorrect operation for up to two counter overflow periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period. also, using a tim overfl ow interrupt routine to write a new, smaller output compare value may cause the compare to be missed. the tim may pass the new value before it is written. use the following methods to synchronize unbuffer ed changes in the output compare value on channel x: when changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current output compare pulse. the interrupt rout ine has until the end of the counter overflow period to write the new value. when changing to a larger output compare value, enable tim overflow interrupts and write the new value in the tim overflow interrupt routine. the tim overflow interrupt occurs at the end of the current counter overflow period. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. 18.4.3.2 buffered output compare channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the tch0 pin. the tim channel registers of t he linked pair alternately control the output. setting the ms0b bit in tim channel 0 status and control register (tsc 0) links channel 0 and channel 1. the output compare value in the tim channel 0 register s initially controls the output on the tch0 pin. writing to the tim channel 1 registers enables the tim channel 1 registers to synchronously control the output after the tim overflows. at each subsequent ov erflow, the tim channel registers (0 or 1) that control the output are the ones written to last. ts c0 controls and monitors the buffered output compare function, and tim channel 1 status and control register (tsc1) is unused. while the ms0b bit is set, the channel 1 pin, tch1, is available as a general-purpose i/o pin. note in buffered output compare operation, do not write new output compare values to the currently active channel registers. user software should track the currently active channel to prevent writing a new value to the active channel. writing to the active channel registers is the same as generating unbuffered output compares.
functional description mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 209 18.4.4 pulse widt h modulation (pwm) by using the toggle-on-overflow feature with an output compare channel, the tim can generate a pwm signal. the value in the tim counter modulo regi sters determines the period of the pwm signal. the channel pin toggles when the counter reaches the valu e in the tim counter modulo registers. the time between overflows is the period of the pwm signal. as figure 18-4 shows, the output compare value in the tim channel registers determines the pulse width of the pwm signal. the time between overflow and out put compare is the pulse width. program the tim to clear the channel pin on output compare if the state of the pwm pulse is 1 (elsxa = 0). program the tim to set the pin if the state of the pwm pulse is 0 (elsxa = 1). the value in the tim counter modulo registers and the selected prescaler output determines the frequency of the pwm output. the frequency of an 8-bit pwm signal is variable in 256 increments. writing $00ff (255) to the tim counter modulo registers produces a pwm period of 256 times the internal bus clock period if the prescaler select value is 000. see 18.9.1 tim status and control register . figure 18-4. pwm period and pulse width the value in the tim channel registers determines the pulse width of the pwm output. the pulse width of an 8-bit pwm signal is variable in 256 increments. writing $0080 (128) to the tim channel registers produces a duty cycle of 128/256 or 50%. 18.4.4.1 unbuffered pwm signal generation any output compare channel can generate unbuffered pwm pulses as described in 18.4.4 pulse width modulation (pwm) . the pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currently in the tim channel registers. an unsynchronized write to the tim channel registers to change a pulse width value could cause incorrect operation for up to two pwm periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new va lue prevents any compare during that pwm period. also, using a tim overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. the tim may pass the new value before it is written. use the following methods to synchronize unbuffer ed changes in the pwm pulse width on channel x: when changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current pulse. the interrupt routine has until the end of the pwm period to write the new value. tchx period pulse width overflow overflow overflow output compare output compare output compare tchx polarity = 1 (elsxa = 0) polarity = 0 (elsxa = 1)
timer interface modu les (tim1 and tim2) mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 210 freescale semiconductor when changing to a longer pulse width, enable tim overflow interrupts and write the new value in the tim overflow interrupt routine. the tim overflow interrupt occurs at the end of the current pwm period. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same pwm period. note in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. toggling on output compare also can cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. 18.4.4.2 buffered pwm signal generation channels 0 and 1 can be linked to form a buffered pwm channel whose output appears on the tch0 pin. the tim channel registers of the linked pair alternately control the pulse width of the output. setting the ms0b bit in tim channel 0 status and control register (tsc 0) links channel 0 and channel 1. the tim channel 0 registers initially control the pulse width on the tch0 pin. writing to the tim channel 1 registers enables the tim channel 1 registers to synchronously control the pulse width at the beginning of the next pwm period. at each subsequent overflow, the tim channel registers (0 or 1) that control the pulse width are the ones written to last. tsc0 controls and monitors the buffered pwm function, and tim channel 1 status and control register (tsc1) is unused. while the ms0b bit is set, the channel 1 pin, tch1, is available as a general-purpose i/o pin. note in buffered pwm signal generation, do not write new pulse width values to the currently active channel regist ers. user software should track the currently active channel to prevent writing a new value to the active channel. writing to the active channel registers is the same as generating unbuffered pwm signals. 18.4.4.3 pwm initialization to ensure correct operation when generating unbuffered or buffered pwm signals, use the following initialization procedure: 1. in the tim status and control register (tsc): a. stop the tim counter by setting the tim stop bit, tstop. b. reset the tim counter and prescaler by setting the tim reset bit, trst. 2. in the tim counter modulo registers (tmodh:tmodl), write the value for the required pwm period. 3. in the tim channel x registers (tchxh:tchxl), write the value for the required pulse width. 4. in tim channel x status and control register (tscx): a. write 0:1 (for unbuffered output compare or pwm signals) or 1:0 (for buffered output compare or pwm signals) to the mode se lect bits, msxb:msxa. see table 18-3 . b. write 1 to the toggle-on-overflow bit, tovx. c. write 1:0 (polarity 1 ? to clear output on compare) or 1:1 (polarity 0 ? to set output on compare) to the edge/level select bits, elsxb:elsxa. the output action on compare must force the output to the complement of the pulse width level. see table 18-3 .
interrupts mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 211 note in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. toggling on output compare can also cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. 5. in the tim status control register (tsc), clear the tim stop bit, tstop. setting ms0b links channels 0 and 1 and configures them for buffered pwm operation. the tim channel 0 registers (tch0h:tch0l) initially control the buffered pwm output. tim channel 0 status and control register (tsc0) controls and monito rs the pwm signal from the linked channels. clearing the toggle-on-overflow bit, tovx, inhibits output toggles on tim overflows. subsequent output compares try to force the output to a state it is already in and have no effect. the result is a 0% duty cycle output. setting the channel x maximum duty cycle bit (chxmax) and setting the tovx bit generates a 100% duty cycle output. see 18.9.4 tim channel status and control registers . 18.5 interrupts the following tim sources can generate interrupt requests: tim overflow flag (tof) ? the tof bit is set when the tim counter reaches the modulo value programmed in the tim counter modulo registers. the tim overflow interrupt enable bit, toie, enables tim overflow cpu interrupt requests. tof and toie are in the tim status and control register. tim channel flags (ch1f:ch0f) ? the chxf bit is set when an input capture or output compare occurs on channel x. channel x tim cpu interr upt requests are controlled by the channel x interrupt enable bit, chxie. channel x tim cpu interrupt requests are enabled when chxie = 1. chxf and chxie are in the tim channel x status and control register. 18.6 low-power modes the wait and stop instructions put the mcu in low power- consumption standby modes. 18.6.1 wait mode the tim remains active after the execution of a wait instruction. in wait mode, the tim registers are not accessible by the cpu. any enabled cpu interrupt request from the tim can bring the mcu out of wait mode. if tim functions are not required during wait mode, r educe power consumption by stopping the tim before executing the wait instruction. 18.6.2 stop mode the tim is inactive after the execution of a stop instruction. the stop instruction does not affect register conditions or the state of the tim counter. tim operation resumes when the mcu exits stop mode after an external interrupt.
timer interface modu les (tim1 and tim2) mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 212 freescale semiconductor 18.7 tim during break interrupts a break interrupt stops the tim counter. the system integration module (sim) controls whethe r status bits in other modules can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bits during the break state. see 15.7.3 sim break flag control register . to allow software to clear status bits during a break in terrupt, write a 1 to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break state, write a 0 to the bcfe bit. with bcfe at 0 (its default state), software can read and write i/o registers during the brea k state without affecting status bits. some status bits have a 2-step read/write clearing procedure. if so ftware does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is at 0. after the break, doing the second step clears the status bit. 18.8 i/o signals port d shares four of its pins with the tim. th e four tim channel i/o pins are t1ch0, t1ch1, t2ch0, and t2ch1 as described in 18.3 pin name conventions . each channel i/o pin is programmable independently as an input capture pin or an output compare pin. t1ch0 and t2ch0 can be configured as buffered output compare or buffered pwm pins. 18.9 i/o registers note references to either timer 1 or timer 2 may be made in the following text by omitting the timer number. for example, tsc may generically refer to both t1sc and t2sc. these i/o registers control and monitor operation of the tim: tim status and control register (tsc) tim counter registers (tcnth:tcntl) tim counter modulo registers (tmodh:tmodl) tim channel status and control registers (tsc0, tsc1) tim channel registers (tch0h:tch0l, tch1h:tch1l) 18.9.1 tim status and control register the tim status and control register (tsc): enables tim overflow interrupts flags tim overflows stops the tim counter resets the tim counter prescales the tim counter clock
i/o registers mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 213 tof ? tim overflow flag bit this read/write flag is set when the tim counter reaches the modulo value programmed in the tim counter modulo registers. clear tof by reading the tim status and control register when tof is set and then writing a 0 to tof. if another tim overflow occurs before the clearing sequence is complete, then writing 0 to tof has no effect. therefore, a tof interrupt request cannot be lost due to inadvertent clearing of tof. reset clears th e tof bit. writing a 1 to tof has no effect. 1 = tim counter has reached modulo value 0 = tim counter has not reached modulo value toie ? tim overflow interrupt enable bit this read/write bit enables tim overflow interrupt s when the tof bit becom es set. reset clears the toie bit. 1 = tim overflow interrupts enabled 0 = tim overflow interrupts disabled tstop ? tim stop bit this read/write bit stops the tim counter. counting resumes when tstop is cleared. reset sets the tstop bit, stopping the tim counter until software clears the tstop bit. 1 = tim counter stopped 0 = tim counter active note do not set the tstop bit before entering wait mode if the tim is required to exit wait mode. trst ? tim reset bit setting this write-only bit resets the tim counter and the tim prescaler. setting trst has no effect on any other registers. counting resumes from $0000. trst is cleared automatically after the tim counter is reset and always reads as 0. reset clears the trst bit. 1 = prescaler and tim counter cleared 0 = no effect note setting the tstop and trst bits simultaneously stops the tim counter at a value of $0000. ps[2:0] ? prescaler select bits these read/write bits select one of the seven prescaler outputs as the input to the tim counter as table 18-2 shows. reset clears the ps[2:0] bits. address: t1sc, $0020 and t2sc, $002b bit 7654321bit 0 read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 = unimplemented figure 18-5. tim status and control register (tsc)
timer interface modu les (tim1 and tim2) mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 214 freescale semiconductor 18.9.2 tim counter registers the two read-only tim counter registers contain the high and low bytes of the value in the tim counter. reading the high byte (tcnth) latches the contents of the low byte (tcntl) into a buffer. subsequent reads of tcnth do not affect the latched tcntl value until tcntl is read. reset clears the tim counter registers. setting the tim reset bit (trst) also clears the tim counter registers. note if you read tcnth during a break interrupt, be sure to unlatch tcntl by reading tcntl before exiting the break interrupt. otherwise, tcntl reta ins the value latched during the break. 18.9.3 tim counter modulo registers the read/write tim modulo register s contain the modulo value for the tim counter. when the tim counter reaches the modulo value, the overflow flag (tof ) becomes set, and the tim counter resumes counting from $0000 at the next timer clock. writing to the hi gh byte (tmodh) inhibits the tof bit and overflow interrupts until the low byte (tmodl) is written. reset sets the tim counter modulo registers. table 18-2. prescaler selection ps2 ps1 ps0 tim clock source 0 0 0 internal bus clock 1 0 0 1 internal bus clock 2 0 1 0 internal bus clock 4 0 1 1 internal bus clock 8 1 0 0 internal bus clock 16 1 0 1 internal bus clock 32 1 1 0 internal bus clock 64 1 1 1 not available address: t1cnth, $0021 and t2cnth, $002c bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 = unimplemented figure 18-6. tim counter registers high (tcnth) address: t1cntl, $0022 and t2cntl, $002d bit 7654321bit 0 read:bit 7654321bit 0 write: reset:00000000 = unimplemented figure 18-7. tim counter registers low (tcntl)
i/o registers mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 215 note reset the tim counter before writing to the tim counter modulo registers. 18.9.4 tim channel status and control registers each of the tim channel status and control registers: flags input captures and output compares enables input capture and output compare interrupts selects input capture, output compare, or pwm operation selects high, low, or toggling output on output compare selects rising edge, falling edge, or any edge as the active input capture trigger selects output toggling on tim overflow selects 0% and 100% pwm duty cycle selects buffered or unbuffered output compare/pwm operation address: t1modh, $0023 and t2modh, $002e bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 figure 18-8. tim counter modulo register high (tmodh) address: t1modl, $0024 and t2modl, $002f bit 7654321bit 0 read: bit 7654321bit 0 write: reset:11111111 figure 18-9. tim counter modulo register low (tmodl) address: t1sc0, $0025 and t2sc0, $0030 bit 7654321bit 0 read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 figure 18-10. tim channel 0 status and control register (tsc0) address: t1sc1, $0028 and t2sc1, $0033 bit 7654321bit 0 read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 = unimplemented figure 18-11. tim channel 1 status and control register (tsc1)
timer interface modu les (tim1 and tim2) mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 216 freescale semiconductor chxf ? channel x flag bit when channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. when channel x is an output com pare channel, chxf is set when the value in the tim counter registers matches the value in the tim channel x registers. when tim cpu interrupt requests are enabled (chx ie = 1), clear chxf by reading tim channel x status and control register with chxf set and then writing a 0 to chxf. if another interrupt request occurs before the clearing sequence is complete, then writing 0 to chxf has no effect. therefore, an interrupt request cannot be lost due to inadvertent clearing of chxf. reset clears the chxf bit. writing a 1 to chxf has no effect. 1 = input capture or output compare on channel x 0 = no input capture or output compare on channel x chxie ? channel x interrupt enable bit this read/write bit enables tim cpu interrupt service requests on channel x. reset clears the chxie bit. 1 = channel x cpu interrupt requests enabled 0 = channel x cpu interrupt requests disabled msxb ? mode select bit b this read/write bit selects buffered output compare/pwm operation. msxb exists only in the tim1 channel 0 and tim2 channel 0 status and control registers. setting ms0b disables the channel 1 status and cont rol register and reverts tch1 to general-purpose i/o. reset clears the msxb bit. 1 = buffered output compare/pwm operation enabled 0 = buffered output compare/pwm operation disabled msxa ? mode select bit a when elsxb:elsxa 0:0, this read/write bit selects ei ther input capture operation or unbuffered output compare/pwm operation. see table 18-3 . 1 = unbuffered output compare/pwm operation 0 = input capture operation when elsxb:elsxa = 0:0, this read/write bit selects the initial output level of the tchx pin. see table 18-3 . reset clears the msxa bit. 1 = initial output level low 0 = initial output level high note before changing a channel function by writing to the msxb or msxa bit, set the tstop and trst bits in the tim status and control register (tsc). elsxb and elsxa ? edge/level select bits when channel x is an input capture channel, these read/ write bits control the active edge-sensing logic on channel x. when channel x is an output com pare channel, elsxb and elsxa control the channel x output behavior when an output compare occurs. when elsxb and elsxa are both clear, channel x is not connected to port d, and pin ptdx/tchx is available as a general-purpose i/o pin. table 18-3 shows how elsxb and elsxa work. reset clears the elsxb and elsxa bits. note before enabling a tim channel register for input capture operation, make sure that the ptdx/tchx pin is st able for at least two bus clocks.
i/o registers mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 217 tovx ? toggle on overflow bit when channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the tim counter overflows. when c hannel x is an input capture channel, tovx has no effect. reset clears the tovx bit. 1 = channel x pin toggles on tim counter overflow 0 = channel x pin does not toggle on tim counter overflow note when tovx is set, a tim counter ov erflow takes precedence over a channel x output compare if both occur at the same time. chxmax ? channel x maximum duty cycle bit when the tovx bit is at 1, setting the chxmax bit forces the duty cycle of buffered and unbuffered pwm signals to 100%. as figure 18-12 shows, the chxmax bit takes effect in the cycle after it is set or cleared. the output stays at the 100% duty cycle level until the cycle after chxmax is cleared. note the 100% pwm duty cycle is defined as a continuous high level if the pwm polarity is 1 and a continuous low level if the pwm polarity is 0. conversely, a 0% pwm duty cycle is defined as a continuous low level if the pwm polarity is 1 and a continuous high level if the pwm polarity is 0. figure 18-12. chxmax latency table 18-3. mode, edge, and level selection msxb msxa elsxb elsxa mode configuration x0 0 0 output preset pin under port control; initial output level high x 1 0 0 pin under port control; initial output level low 00 0 1 input capture capture on rising edge only 0 0 1 0 capture on falling edge only 0 0 1 1 capture on rising or falling edge 01 0 0 output compare or pwm software compare only 0 1 0 1 toggle output on compare 0 1 1 0 clear output on compare 0 1 1 1 set output on compare 1x 0 1 buffered output compare or buffered pwm toggle output on compare 1 x 1 0 clear output on compare 1 x 1 1 set output on compare output overflow tchx period chxmax overflow overflow overflow overflow compare output compare output compare output compare
timer interface modu les (tim1 and tim2) mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 218 freescale semiconductor 18.9.5 tim channel registers these read/write registers contain the captured tim counter value of the input capture function or the output compare value of the output compare function. the state of the tim channel registers after reset is unknown. in input capture mode (msxb:msxa = 0:0), reading th e high byte of the tim channel x registers (tchxh) inhibits input captures until the low byte (tchxl) is read. in output compare mode (msxb:msxa 0:0), writing to the high byte of the tim channel x registers (tchxh) inhibits output compares until the low byte (tchxl) is written. address: t1ch0h, $0026 and t2ch0h, $0031 bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset figure 18-13. tim channel 0 register high (tch0h) address: t1ch0l, $0027 and t2ch0l $0032 bit 7654321bit 0 read: bit 7654321bit 0 write: reset: indeterminate after reset figure 18-14. tim channel 0 register low (tch0l) address: t1ch1h, $0029 and t2ch1h, $0034 bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset figure 18-15. tim channel 1 register high (tch1h) address: t1ch1l, $002a and t2ch1l, $0035 bit 7654321bit 0 read: bit 7654321bit 0 write: reset: indeterminate after reset figure 18-16. tim channel 1 register low (tch1l)
mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 219 chapter 19 development support 19.1 introduction this section describes the break module, the mo nitor module (mon), and the monitor mode entry methods. 19.2 break module (brk) the break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program. features of the break module include: accessible input/output (i/o) registers during the break interrupt central processor unit (cpu) generated break interrupts software-generated break interrupts computer operating properly (cop ) disabling during break interrupts 19.2.1 functional description when the internal address bus matches the value writt en in the break address registers, the break module issues a breakpoint signal (bkpt ) to the system integration module (sim). the sim then causes the cpu to load the instruction register with a software interrupt instruction (swi). the program counter vectors to $fffc and $fffd ($fefc and $fefd in monitor mode). the following events can cause a break interrupt to occur: a cpu generated address (the address in the program counter) matches the contents of the break address registers. software writes a 1 to the brka bit in the break status and control register. when a cpu generated address matches the contents of t he break address registers, the break interrupt is generated. a return-from-interrupt instruction (rti) in the break routine ends the break interrupt and returns the microcontroller unit (mcu) to normal operation. figure 19-1 shows the structure of the break module. figure 19-2 provides a summary of the i/o registers. when the internal address bus matches the value writt en in the break address registers or when software writes a 1 to the brka bit in the break status and c ontrol register, the cpu starts a break interrupt by: loading the instruction register with the swi instruction loading the program counter with $fffc and $fffd ($fefc and $fefd in monitor mode)
development support mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 220 freescale semiconductor figure 19-1. break module block diagram the break interrupt timing is: when a break address is placed at the address of the instruction opcode, the instruction is not executed until after completion of the break interrupt routine. when a break address is placed at an address of an instruction operand, the instruction is executed before the break interrupt. when software writes a 1 to the brka bit, the break interrupt occurs just before the next instruction is executed. addr.register name bit 7654321bit 0 $fe00 break status register (sbsr) see page 222. read: rrrrrr sbsw r write: note (1) reset: 0 $fe02 reserved read: rrrrrrrr write: reset:00000000 $fe03 break flag control register (sbfcr) see page 223. read: bcferrrrrrr write: reset: 0 $fe09 break address high register (brkh) see page 222. read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:00000000 $fe0a break address low register (brkl) see page 222. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $fe0b break status and control register (brkscr) see page 221. read: brke brka 000000 write: reset:00000000 1. writing a 0 clears sbsw. = unimplemented r = reserved figure 19-2. break i/o register summary address bus[15:8] address bus[7:0] 8-bit comparator 8-bit comparator control break address register low break address register high address bus[15:0] bkpt (to sim)
break module (brk) mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 221 by updating a break address and clearing the brka bit in a break interrupt routine, a break interrupt can be generated continuously. caution a break address should be placed at the address of the instruction opcode. when software does not change the break address and clears the brka bit in the first break interrupt routi ne, the next break interrupt will not be generated after exiting the interrupt routine even when the internal address bus matches the value written in the break address registers. 19.2.1.1 flag protection during break interrupts the system integration module (sim) controls whether or not module status bits can be cleared during the break state. the bcfe bit in the break flag control register (bfcr) enables software to clear status bits during the break state. see 19.2.2.4 break flag control register and the break interrupts subsection for each module. 19.2.1.2 tim during break interrupts a break interrupt stops the timer counter. 19.2.1.3 cop during break interrupts the cop is disabled during a break interrupt when v tst is present on the rst pin. 19.2.2 break module registers these registers control and monitor operation of the break module: break status and control register (brkscr) break address register high (brkh) break address register low (brkl) break status register (sbsr) break flag control register (sbfcr) 19.2.2.1 break status and control register the break status and control register (brkscr) contains break module enable and status bits. brke ? break enable bit this read/write bit enables breaks on break addres s register matches. clear brke by writing a 0 to bit 7. reset clears the brke bit. 1 = breaks enabled on 16-bit address match 0 = breaks disabled address: $fe0b bit 7654321bit 0 read: brke brka 000000 write: reset:00000000 = unimplemented figure 19-3. break status and control register (brkscr)
development support mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 222 freescale semiconductor brka ? break active bit this read/write status and control bit is set when a break address match occurs. writing a 1 to brka generates a break interrupt. clear brka by writing a 0 to it before exiting the break routine. reset clears the brka bit. 1 = break address match 0 = no break address match 19.2.2.2 break address registers the break address registers (brkh and brkl) contai n the high and low bytes of the desired breakpoint address. reset clears the break address registers. 19.2.2.3 break status register the break status register (sbsr) contains a flag to indicate that a break caus ed an exit from wait mode. this register is only used in emulation mode. sbsw ? sim break stop/wait sbsw can be read within the break state swi routine. the user can modify the return address on the stack by subtracting one from it. 1 = wait mode was exited by break interrupt 0 = wait mode was not exited by break interrupt address: $fe09 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 figure 19-4. break address register high (brkh) address: $fe0a bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 figure 19-5. break address register low (brkl) address: $fe00 bit 7654321bit 0 read: rrrrrr sbsw r write: note (1) reset: 0 r = reserved 1. writing a 0 clears sbsw. figure 19-6. break status register (sbsr)
monitor module (mon) mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 223 19.2.2.4 break flag control register the break control register (sbfcr) contains a bit that enables software to clear status bits while the mcu is in a break state. bcfe ? break clear flag enable bit this read/write bit enables software to clear status bi ts by accessing status r egisters while the mcu is in a break state. to clear status bits duri ng the break state, the bcfe bit must be set. 1 = status bits cl earable during break 0 = status bits not clearable during break 19.2.3 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. if enabled, the break module will remain enabled in wait and stop mo des. however, since the internal address bus does not increment in these modes, a break interrupt will never be triggered. 19.3 monitor module (mon) this subsection describes the m onitor module (mon) and the monitor mode entry methods. the monitor allows debugging and programming of the microcontrolle r unit (mcu) through a single-wire interface with a host computer. features include: normal user-mode pin functionality on most pins one pin dedicated to serial communi cation between mcu and host computer standard non-return-to-zero (nrz) communication with host computer 9600 baud communication with host computer execution of code in random-a ccess memory (ram) or rom 19.3.1 functional description figure 19-8 shows a simplified diagram of monitor mode entry. the monitor module receives and execut es commands from a host computer. figure 19-9 shows an example circuit used to enter monito r mode and communicate with a host computer via a standard rs-232 interface. simple monitor commands can access any memory address. in monitor mode, the mcu can execute code downloaded into ram by a host computer wh ile most mcu pins retain normal operating mode functions. all communicati on between the host computer and the mcu is through the pta0 pin. a level-shifting and multiplexing interface is required between pta0 and the host computer. pta0 is used in a wired-or configuration and requires a pullup resistor. address: $fe03 bit 7654321bit 0 read: bcferrrrrrr write: reset: 0 r = reserved figure 19-7. break flag control register (sbfcr)
development support mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 224 freescale semiconductor figure 19-8. simplified monitor mode entry flowchart monitor mode entry por reset pta0 = 1, ptc0 = 1, ptc1 = 0, and pta7 = 0? irq = v tst ? yes no yes no normal user mode normal monitor mode invalid user mode no host sends 8 security bytes is reset por? yes yes no are all security bytes correct? no yes enable rom disable rom execute monitor code does reset occur? conditions from table 19-2 debugging
monitor module (mon) mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 225 figure 19-9. normal monitor mode circuit 19.3.1.1 monitor mode entry table 19-2 shows the pin conditions for entering monitor mo de. as specified in the table, monitor mode may be entered after a power-on reset (por) and w ill allow communication provided the pin and clock conditions are met. the rising edge of the internal rst signal latches the monitor mode. once monitor mode is latched, the values on pta7, ptc0, ptc1, and ptc3 pins can be changed. once out of reset, the mcu waits for the host to send eight security bytes (see 19.3.2 security ). after the security bytes, the mcu sends a break signal (10 consecut ive 0s) to the host, indicating that it is ready to receive a command. 19.3.1.2 monitor vectors in monitor mode, the mcu uses different vectors for reset, swi (software interrupt), and break interrupt than those for user mode. the alternate vectors are in the $fe page instead of the $ff page and allow code execution from the internal monitor firmware in stead of user code. the cop module is disabled in monitor mode as long as v tst is applied to either the irq pin or the rst pin. table 19-1 summarizes the differences between user mode and monitor mode regarding vectors. 10 k 10 k nc 10 k rst irq pta0 8 7 db9 2 3 5 16 15 2 6 10 9 v dd 1 f max232 v+ v? v dd 1 f + 1 2 3 4 5 6 74hc125 74hc125 10 k ? v ss 0.1 f v dd c1+ c1? 5 4 1 f c2+ c2? + 3 1 1 f + + + 1 f v dd v cc gnd 1 k ? osc1 9.8304 mhz v dda ptc3 ptc0 ptc1 v ssa v dd mc68hc08gp32a/mc68hc08gp16a 9.1 v 10 k pta7
development support mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 226 freescale semiconductor 19.3.1.3 data format communication with the monitor rom is in standard non-return-to-zero (nrz) ma rk/space data format. transmit and receive baud rates must be identical. figure 19-10. monitor data format 19.3.1.4 break signal a start bit (0) followed by nine 0 bits is a break signal . when the monitor receives a break signal, it drives the pta0 pin high for the duration of two bits and then echoes back the break signal. figure 19-11. break transaction table 19-1. mode differences modes functions cop reset vector high reset vector low break vector high break vector low swi vector high swi vector low user enabled $fffe $ffff $fffc $fffd $fffc $fffd monitor disabled (1) 1. if the high voltage (v tst ) is removed from the irq pin while in monitor mode, the sim asserts its cop enable output. the cop is a mask option enabled or disabled by the copd bit in the mask option register. (see 20.5 5.0-v dc electrical char- acteristics .) $fefe $feff $fefc $fefd $fefc $fefd bit 5 start bit bit 1 next stop bit start bit bit 2 bit 3 bit 4 bit 7 bit 0 bit 6 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 missing stop bit 2-stop bit delay before zero echo
monitor module (mon) mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 227 table 19-2. mode selection mode irq rst serial comm. mode selection divider pll cop communication speed comments pta0 pta7 ptc0 ptc1 ptc3 external clock bus frequency baud rate monitor v tst v dd or v tst 10 1 0 0offdisabled 4.9152 mhz 2.4576 mhz 9600 ptc3 determines frequency divider v tst v dd or v tst 10 1 0 1offdisabled 9.8304 mhz 2.4576 mhz 9600 user v dd or v ss v dd x x x x x x enabled x x x mon08 function [pin no.] v tst [6] rst [4] com [8] ssel [10] mod0 [12] mod1 [14] div4 [16] osc1 [13] 1. pta0 must have a pullup resistor to v dd in monitor mode. 2. communication speed in the table is an example to obtain a baud rate of 9600. baud rate using external oscillator is bus frequency / 256. 3. external clock is a 4.9152 or 9.8304 mhz canned oscillator on osc1. 4. x = don?t care 5. mon08 pin refers to p&e microcomputer systems? mon08-cyclone 2 by 8-pin connector. nc 1 2 gnd nc 3 4 rst nc 5 6 irq nc 7 8 pta0 nc 9 10 pta7 nc 11 12 ptc0 osc1 13 14 ptc1 v dd 15 16 ptc3
development support mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 228 freescale semiconductor 19.3.1.5 commands the monitor rom firmware uses these commands: read (read memory) write (write memory) iread (indexed read) iwrite (indexed write) readsp (read stack pointer) run (run user program) the monitor rom firmware echoes each received byte back to the pta0 pin for error checking. an 11-bit delay at the end of each command allows the host to send a break character to cancel the command. a delay of two bit times occurs before each echo and before read, iread, or readsp data is returned. the data returned by a read command appears after the echo of the last byte of the command. note wait one bit time after each echo before sending the next byte. figure 19-12. read transaction figure 19-13. write transaction read read echo from host address high address high address low address low data return 13, 2 11 4 4 notes: 2 = data return delay, approximately 2 bit times 3 = cancel command delay, 11 bit times 4 = wait 1 bit time before sending next byte. 44 1 = echo delay, approximately 2 bit times write write echo from host address high address high address low address low data data notes: 2 = cancel command delay, 11 bit times 3 = wait 1 bit time before sending next byte. 11 3 11 3 3 32, 3 1 = echo delay, approximately 2 bit times
monitor module (mon) mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 229 a brief description of each monitor mode command is given in table 19-3 through table 19-8 . table 19-3. read (read memory) command description read byte from memory operand 2-byte address in high-byte:low-byte order data returned returns contents of specified address opcode $4a command sequence table 19-4. write (write memory) command description write byte to memory operand 2-byte address in high-byte:low-by te order; low byte followed by data byte data returned none opcode $49 command sequence table 19-5. iread (indexed read) command description read next 2 bytes in me mory from last address accessed operand 2-byte address in high byte:low byte order data returned returns contents of next two addresses opcode $1a command sequence read read echo sent to monitor address high address high address low data return address low write write echo from host address high address high address low address low data data iread iread echo data return data from host
development support mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 230 freescale semiconductor a sequence of iread or iwrite commands can acce ss a block of memory sequentially over the full 64-kbyte memory map. table 19-6. iwrite (indexed write) command description write to la st address accessed + 1 operand single data byte data returned none opcode $19 command sequence table 19-7. readsp (read stack pointer) command description reads stack pointer operand none data returned returns incremented stack pointer value (sp + 1) in high-byte:low-byte order opcode $0c command sequence table 19-8. run (run user program) command description executes pulh and rti instructions operand none data returned none opcode $28 command sequence iwrite iwrite echo from host data data readsp readsp echo from host sp return sp high low run run echo from host
monitor module (mon) mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 231 the mcu executes the swi and pshh instructions when it enters monitor mode. the run command tells the mcu to execute the pulh and rti instru ctions. before sending th e run command, the host can modify the stacked cpu registers to prepare to run the host program. the readsp command returns the incremented stack pointer value, sp + 1. the high and low bytes of the program counter are at addresses sp + 5 and sp + 6. figure 19-14. stack pointer at monitor mode entry 19.3.2 security a security feature discourages unauthorized reading of rom locations while in monitor mode. the host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $fff6?$fffd. locations $fff6?$fffd contain user-defined data. note do not leave locations $fff6?$fffd bl ank. for security reasons, program locations $fff6?$fffd even if they are not used for vectors. during monitor mode entry, the mcu waits after the powe r-on reset for the host to send the eight security bytes on pin pta0. if the received bytes match those at locations $fff6?$fffd, the host bypasses the security feature and can read all rom locations and execute code from rom. se curity remains bypassed until a power-on reset occurs. if the reset was not a power-on reset, security remains bypassed and security code entry is not required. see figure 19-15 . upon power-on reset, if the received bytes of the security code do not match the data at locations $fff6?$fffd, the host fails to bypass the security feature. the mcu remains in monitor mode, but reading a rom location returns an invalid value and trying to execute code from rom causes an illegal address reset. after receiving the eight security byte s from the host, the mcu transmits a break character, signifying that it is ready to receive a command. note the mcu does not transmit a break char acter until after the host sends the eight security bytes. if the security sequence fails, the device should be reset by a power-on reset and brought up in monitor mode to attempt another entry. condition code register accumulator low byte of index register high byte of program counter low byte of program counter sp + 1 sp + 2 sp + 3 sp + 4 sp + 5 sp sp + 6 high byte of index register sp + 7
development support mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 232 freescale semiconductor figure 19-15. monitor mode entry timing 19.3.3 baud rate with a 9.8304 mhz canned oscillator and the ptc3 pi n high during reset, data is transferred between the monitor and host at 9600 baud. table 19-9 lists external frequencies required to achieve a standard baud rate of 9600 bps. other standard baud rates can be accomplished using proporti onally higher or lower frequency generators. table 19-9. monitor baud rate selection external frequency ptc3 bus frequency baud rate 4.9152 mhz 0 2.4576 mhz 9600 9.8304 mhz 1 2.4576 mhz 9600 byte 1 byte 1 echo byte 2 byte 2 echo byte 8 byte 8 echo command command echo pa0 rst v dd 4096 + 32 cgmxclk cycles 1 3 1 1 2 1 break notes: 2 = data return delay, approximately 2 bit times 3 = wait 1 bit time before sending next byte 3 from host from mcu 1 = echo delay, approximately 2 bit times 4 4 = wait until clock is stable and monitor runs
mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 233 chapter 20 electrical specifications 20.1 introduction this section contains electrical and timing specifications. 20.2 absolute maximum ratings maximum ratings are the extreme limits to which t he microcontroller unit (mcu) can be exposed without permanently damaging it. note this device is not guaranteed to operate properly at the maximum ratings. refer to 20.5 5.0-v dc electrical characteristics for guaranteed operating conditions . note this device contains circuitry to pr otect the inputs against damage due to high static voltages or electric fields ; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. for proper operation, it is recommended that v in and v out be constrained to the range v ss (v in or v out ) v dd . reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either v ss or v dd ). characteristic (1) 1. voltages referenced to v ss symbol value unit supply voltage v dd ?0.3 to + 6.0 v input voltage v in v ss ? 0.3 to v dd + 0.3 v maximum current per pin excluding v dd , v ss , and ptc0?ptc4 i 15 ma maximum current for pins ptc0?ptc4 i ptc0?ptc4 25 ma maximum current into v dd i mvdd 150 ma maximum current out of v ss i mvss 150 ma storage temperature t stg ?55 to +150 c
electrical specifications mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 234 freescale semiconductor 20.3 functional operating range 20.4 thermal characteristics 20.5 5.0-v dc electrical characteristics characteristic symbol value unit cv m operating temperature range t a ?40 to +85 ?40 to +105 ?40 to +125 c operating voltage range v dd 3 v 10% 5 v 10% 3 v 10% 5 v 10% ? 5 v 10% v characteristic symbol value unit thermal resistance 42-pin sdip 44-pin qfp ja 60 95 c/w i/o pin power dissipation p i/o user determined w power dissipation (1) 1. power dissipation is a function of temperature. p d p d = (i dd v dd ) + p i/o = k/(t j + 273 c ) w constant (2) 2. k is a constant unique to the device. k can be determined for a known t a and measured p d . with this value of k, p d and t j can be determined for any value of t a . k p d (t a + 273 c) + p d 2 ja w / c average junction temperature t j t a + (p d ja ) c characteristic (1) symbol min typ (2) max unit output high voltage (i load = ?2.0 ma) all i/o pins (i load = ?10.0 ma) all i/o pins (i load = ?10.0 ma) pins ptc0?ptc4 only maximum combined i oh for port c, port e, port ptd0?ptd3 maximum combined i oh for port ptd4?ptd7, port a, port b maximum total i oh for all port pins v oh v oh v oh i oh1 i oh2 i oht v dd ? 0.8 v dd ? 1.5 v dd ? 0.8 ? ? ? ? ? ? ? ? ? ? ? ? 50 50 100 v v v ma ma ma output low voltage (i load = 1.6 ma) all i/o pins (i load = 10 ma) all i/o pins (i load = 15 ma) pins ptc0?ptc4 only maximum combined i ol for port c, port e, port ptd0?ptd3 maximum combined i ol for port ptd4?ptd7, port a, port b maximum total i ol for all port pins v ol v ol v ol i ol1 i ol2 i olt ? ? ? ? ? ? ? ? ? ? ? ? 0.4 1.5 1.0 50 50 100 v v v ma ma ma ? continued on next page
5.0-v dc electrical characteristics mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 235 input high voltage all ports, irq , rst , osc1 v ih 0.7 v dd ? v dd v input low voltage all ports, irq , rst , osc1 v il v ss ? 0.2 v dd v v dd supply current run (3) wait (4) stop (5) 25 c 25 c with tbm enabled (6) 25 c with lvi and tbm enabled (6) ?40 c to 85 c ?40 c to 85 c with tbm enabled (6) ?40 c to 85 c with lvi and tbm enabled (6) i dd ? ? ? ? ? ? ? ? 15 4 2 20 300 ? 50 500 20 8 ? ? ? 35 ? ? ma ma a a a a a a i/o ports hi-z leakage current (7) i il ?10 ? +10 a input current i in ?1 ? +1 a pullup resistors (as input only) ports pta7/kbd7 ?pta0/kbd0 , ptc6?ptc0, ptd7/t2ch1?ptd0/ss r pu 20 45 65 k ? capacitance ports (as input or output) c out c in ? ? ? ? 12 8 pf monitor mode entry voltage v tst v dd + 2.5 ?9.1v low-voltage inhibit, trip falling voltage v tripf 3.90 4.25 4.50 v low-voltage inhibit, trip rising voltage v tripr 4.00 4.35 4.60 v low-voltage inhibit reset/recover hysteresis (v tripf + v hys = v tripr ) v hys ?100 ?mv por rearm voltage (8) v por 0 ? 100 mv por reset voltage (9) v porrst 0 700 800 mv por rise time ramp rate (10) r por 0.035 ? ? v/ms 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h , unless otherwise noted 2. typical values reflect average measur ements at midpoint of voltage range, 25 c only. 3. run (operating) i dd measured using external square wave clock source (f osc = 32.8 mhz). all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. c l = 20 pf on osc2. all ports configur ed as inputs. osc2 capacitance linearly affects run i dd . measured with all modules enabled. 4. wait i dd measured using external square wave clock source (f osc = 32.8 mhz). all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. c l = 20 pf on osc2. all ports configured as inputs. osc2 capacitance linearly affects wait i dd . measured with pll and lvi enabled. 5. stop i dd is measured with osc1 = v ss . 6. stop i dd with tbm enabled is measured using an external square wave clock source (f osc = 32.8 mhz). all inputs 0.2v from rail. no dc loads. less than 100 pf on all outputs. all inputs configured as inputs. 7. pullups and pulldowns are disabled. port b leakage is specified in 20.12 adc characteristics . 8. maximum is highest vo ltage that por is guaranteed. 9. maximum is highest vo ltage that por is possible. 10. if minimum v dd is not reached before the internal por reset is released, rst must be driven low externally until minimum v dd is reached. characteristic (1) symbol min typ (2) max unit
electrical specifications mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 236 freescale semiconductor 20.6 3.0-v dc electrical characteristics characteristic (1) symbol min typ (2) max unit output high voltage (i load = ?0.6 ma) all i/o pins (i load = ?4.0 ma) all i/o pins (i load = ?4.0 ma) pins ptc0?ptc4 only maximum combined i oh for port c, port e, port ptd0?ptd3 maximum combined i oh for port ptd4?ptd7, port a, port b maximum total i oh for all port pins v oh v oh v oh i oh1 i oh2 i oht v dd ? 0.3 v dd ? 1.0 v dd ? 0.5 ? ? ? ? ? ? ? ? ? ? ? ? 30 30 60 v v v ma ma ma output low voltage (i load = 0.5 ma) all i/o pins (i load = 6.0 ma) all i/o pins (i load = 10.0 ma) pins ptc0?ptc4 only maximum combined i ol for port c, port e, port ptd0?ptd3 maximum combined i ol for port ptd4?ptd7, port a, port b maximum total i ol for all port pins v ol v ol v ol i ol1 i ol2 i olt ? ? ? ? ? ? ? ? ? ? ? ? 0.3 1.0 0.8 30 30 60 v v v ma ma ma input high voltage all ports, irq , rst , osc1 v ih 0.7 v dd ? v dd v input low voltage all ports, irq , rst , osc1 v il v ss ? 0.3 v dd v v dd supply current run (3) wait (4) stop (5) 25 c 25 c with tbm enabled (6) 25 c with tbm enabled (7) 25 c with lvi and tbm enabled (7) ?40 c to 85 c ?40 c to 85 c with tbm enabled (7) ?40 c to 85 c with lvi and tbm enabled (6) i dd ? ? ? ? ? ? ? ? ? 5.2 1.65 1 12 25 200 ? ? 300 8 4 ? ? ? ? 5 50 ? ma ma a a a a a a a i/o ports hi-z leakage current (8) i il ?10 ? +10 a input current i in ?1 ? +1 a pullup resistors (as input only) ports pta7/kbd7 ?pta0/kbd0 , ptc6?ptc0, ptd7/t2ch1?ptd0/ss r pu 20 45 65 k ? capacitance ports (as input or output) c out c in ? ? ? ? 12 8 pf monitor mode entry voltage v tst v dd + 2.5 ? v dd + 4.5 v ? continued on next page
5.0-v control timing mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 237 20.7 5.0-v control timing low-voltage inhibit, trip falling voltage v tripf 2.45 2.60 2.70 v low-voltage inhibit, trip rising voltage v tripr 2.50 2.66 2.80 v low-voltage inhibit reset/recover hysteresis (v tripf + v hys = v tripr ) v hys ?60 ?mv por rearm voltage (9) v por 0 ? 100 mv por reset voltage (10) v porrst 0 700 800 mv por rise time ramp rate (11) r por 0.02 ? ? v/ms 1. v dd = 3.0 vdc 10%, v ss = 0 vdc, t a = t l to t h , unless otherwise noted 2. typical values reflect average measur ements at midpoint of voltage range, 25 c only. 3. run (operating) i dd measured using external square wave clock source (f osc = 16.4 mhz). all inputs 0.2v from rail. no dc loads. less than 100 pf on all outputs. c l = 20 pf on osc2. all ports configur ed as inputs. osc2 capacitance linearly affects run i dd . measured with all modules enabled. 4. wait i dd measured using external square wave clock source (f osc = 16.4 mhz). all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. c l = 20 pf on osc2. all ports configured as inputs. osc2 capacitance linearly affects wait i dd . measured with pll and lvi enabled. 5. stop i dd is measured with osc1 = v ss . 6. stop i dd with tbm enabled is measured using an external square wave clock source (f osc = 16.4 mhz). all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. all inputs configured as inputs. 7. measured with tbm enabled using 32-khz crystal. 8. pullups and pulldowns are disabled. 9. maximum is highest vo ltage that por is guaranteed. 10. maximum is highest voltage that por is possible. 11. if minimum v dd is not reached before the internal por reset is released, rst must be driven low externally until minimum v dd is reached. characteristic (1) 1. v ss = 0 vdc; timing shown with respect to 20% v dd and 70% v dd unless otherwise noted. symbol min max unit frequency of operation (2) crystal option external clock option (3) 2. see 20.16 clock generation module characteristics for more information. 3. no more than 10% duty cycle deviation from 50% f osc 32 dc (4) 4. some modules may require a minimum frequency greater than dc for proper operation. see appropriate table for this in- formation. 100 32.8 khz mhz internal operating frequency f op (f bus ) ?8.2mhz internal clock period (1/f op )t cyc 122 ? ns rst input pulse width low (5) 5. minimum pulse width reset is guaranteed to be recognized. it is possible for a smaller pulse width to cause a reset. t rl 50 ? ns irq interrupt pulse width low (6) (edge-triggered) 6. minimum pulse width is for guaranteed interrupt. it is possible for a smaller pulse width to be recognized. t ilih 50 ? ns irq interrupt pulse period t ilil note (7) 7. the minimum period, t ilil , should not be less than the number of cycles it takes to execut e the interrupt service routine plus t cyc . ? t cyc characteristic (1) symbol min typ (2) max unit
electrical specifications mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 238 freescale semiconductor 20.8 3.0-v control timing figure 20-1. rst and irq timing characteristic (1) 1. v ss = 0 vdc; timing shown with respect to 20% v dd and 70% v dd unless otherwise noted. symbol min max unit frequency of operation (2) crystal option external clock option (3) 2. see 20.16 clock generation module characteristics for more information. 3. no more than 10% duty cycle deviation from 50% f osc 32 dc (4) 4. some modules may require a minimum frequency greater than dc for proper operation. see appropriate table for this in- formation. 100 16.4 khz mhz internal operating frequency f op (f bus ) ?4.1mhz internal clock period (1/f op )t cyc 244 ? ns rst input pulse width low (5) 5. minimum pulse width reset is guaranteed to be recognized. it is possible for a smaller pulse width to cause a reset. t irl 125 ? ns irq interrupt pulse width low (6) (edge-triggered) 6. minimum pulse width is for guaranteed interrupt. it is possible for a smaller pulse width to be recognized. t ilih 125 ? ns irq interrupt pulse period t ilil note (7) 7. the minimum period, t ilil , should not be less than the number of cycles it takes to execut e the interrupt service routine plus t cyc . ? t cyc rst irq t rl t ilih t ilil
output high-voltage characteristics mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 239 20.9 output high-voltage characteristics figure 20-2. typical high-side driver characteristics ? port pta7?pta0 (v dd = 4.5 vdc) figure 20-3. typical high-side driver characteristics ? port pta7?pta0 (v dd = 2.7 vdc) figure 20-4. typical high-side driver characteristics ? port ptc4?ptc0 (v dd = 4.5 vdc) ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 ?40 0 25 i oh (ma) ?40 v oh (v) 3 3.4 3.6 3.8 4.0 4.2 3.2 85 v oh > v dd ?0.8 v @ i oh = ?2.0 ma v oh > v dd ?1.5 v @ i oh = ?10.0 ma ?25 ?20 ?15 ?10 ?5 0 ?40 0 25 i oh (ma) 1.3 1.7 1.9 2.1 2.3 2.5 1.5 85 v oh (v) v oh > v dd ?0.3 v @ i oh = ?0.6 ma v oh > v dd ?1.0 v @ i oh = ?4.0 ma ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 ?40 0 25 i oh (ma) ?40 v oh (v) 3 3.4 3.6 3.8 4.0 4.2 3.2 85 v oh > v dd ?0.8 v @ i oh = ?10.0 ma
electrical specifications mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 240 freescale semiconductor figure 20-5. typical high-side driver characteristics ? port ptc4?ptc0 (v dd = 2.7 vdc) figure 20-6. typical high-side driver characteristics ? ports ptb7?ptb0, ptc6?ptc5, ptd7?ptd0, and pte1?pte0 (v dd = 5.5 vdc) figure 20-7. typical high-side driver characteristics ? ports ptb7?ptb0, ptc6?ptc5, ptd7?ptd0, and pte1?pte0 (v dd = 2.7 vdc) ?25 ?20 ?15 ?10 ?5 0 ?40 0 25 i oh (ma) 1.3 1.7 1.9 2.1 2.3 2.5 1.5 85 v oh (v) v oh > v dd ?0.5 v @ i oh = ?4.0 ma ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 ?40 0 25 i oh (ma) ?90 v oh (v) 3 3.4 3.6 3.8 4.0 4.2 3.2 85 ?80 4.6 4.4 v oh > v dd ?0.8 v @ i oh = ?2.0 ma v oh > v dd ?1.5 v @ i oh = ?10.0 ma ?25 ?20 ?15 ?10 ?5 0 ?40 0 25 i oh (ma) 1.3 1.7 1.9 2.1 2.3 2.5 1.5 85 v oh (v) v oh > v dd ?0.3 v @ i oh = ?0.6 ma v oh > v dd ?1.0 v @ i oh = ?4.0 ma
output low-voltag e characteristics mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 241 20.10 output low-voltage characteristics figure 20-8. typical low-side driver characteristics ? port pta7?pta0 (v dd = 5.5 vdc) figure 20-9. typical low-side driver characteristics ? port pta7?pta0 (v dd = 2.7 vdc) figure 20-10. typical low-side driver characteristics ? port ptc4?ptc0 (v dd = 4.5 vdc) 5 10 15 20 25 30 35 ?40 0 25 i ol (ma) 0 v ol (v) 0 0.4 0.6 0.8 1.0 1.2 0.2 85 1.4 1.6 v ol < 0.4 v @ i ol = 1.6 ma v ol < 1.5 v @ i ol = 10.0 ma 2 4 6 8 10 12 14 ?40 0 25 i ol (ma) 0 v ol (v) 0.4 0.6 0.8 1.0 1.2 0.2 85 1.4 1.6 v ol < 0.3 v @ i ol = 0.5 ma v ol < 1.0 v @ i ol = 6.0 ma 10 20 30 40 50 60 i ol (ma) 0 v ol (v) 0.4 0.6 0.8 1.0 1.2 1.4 1.6 ?40 0 25 85 v ol < 1.0 v @ i ol = 15 ma
electrical specifications mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 242 freescale semiconductor figure 20-11. typical low-side driver characteristics ? port ptc4?ptc0 (v dd = 2.7 vdc) figure 20-12. typical low-side driver characteristics ? ports ptb7?ptb0, ptc6?ptc5, ptd7?ptd0, and pte1?pte0 (v dd = 5.5 vdc) figure 20-13. typical low-side driver characteristics ? ports ptb7?ptb0, ptc6?ptc5, ptd7?ptd0, and pte1?pte0 (v dd = 2.7 vdc) 5 10 15 20 25 30 ?40 0 25 i ol (ma) 0 v ol (v) 0.40.60.81.01.2 0.2 85 1.4 1.6 v ol < 0.8 v @ i ol = 10 ma 5 10 15 20 25 30 35 ?40 0 25 i ol (ma) 0 v ol (v) 0 0.4 0.6 0.8 1.0 1.2 0.2 85 1.4 1.6 v ol < 0.4 v @ i ol = 1.6 ma v ol < 1.5 v @ i ol = 10.0 ma 2 4 6 8 10 12 14 ?40 0 25 i ol (ma) 0 v ol (v) 0.2 0.4 0.6 0.8 1.0 0 85 1.2 1.6 1.4 v ol < 0.3 v @ i ol = 0.5 ma v ol < 1.0 v @ i ol = 6.0 ma
typical supply currents mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 243 20.11 typical supply currents figure 20-14. typical operating i dd figure 20-15. typical wait mode i dd figure 20-16. typical stop mode i dd 0 2 4 6 8 10 12 123456789 f bus (mhz) i dd (ma) 14 16 5.5 v 3.3 v 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 12 34 567 89 i dd (ma) f bus (mhz) 5.5 v 3.3 v 0 0.2 0.4 0.6 0.8 1.0 1.2 123456789 f bus (mhz) i dd (ma) 1.4 1.6 5.5 v 3.3 v
electrical specifications mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 244 freescale semiconductor 20.12 adc characteristics characteristic (1) 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, v ddad = 5.0 vdc 10%, v ssad = 0 vdc, v refh = 5.0 vdc 10%, v refl = 0 symbol min max unit comments supply voltage v ddad 2.7 (v dd min) 5.5 (v dd max) v v ddad should be tied to the same potential as v dd via separate traces. input voltages v adin 0 v ddad v v adin v refh resolution b ad 88bits absolute accuracy (v refl = 0 v, v refh = v ddad = 5 v 10%) a ad ?1 +1 lsb includes quantization adc internal clock f adic 0.5 1.048 mhz t aic = 1/f adic , tested only at 1 mhz conversion range r ad v refl v refh v v refh = v ddad v refl = v ssad power-up time t adpu 16 t aic cycles conversion time t adc 16 17 t aic cycles sample time (2) 2. source impedances greater than 10 k ? adversely affect internal rc charging time during input sampling. t ads 5? t aic cycles zero input reading (3) 3. zero-input/full-scale reading requires sufficien t decoupling measures for accurate conversions. z adi 00 01 hex v in = v refl full-scale reading (3) f adi fe ff hex v in = v refh input capacitance c adi ? (20) 8 pf not tested input leakage (4) port b 4. the external system error caused by in put leakage current is approximately equal to the product of r source and input current. ??1 +1 a
5.0-v spi characteristics mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 245 20.13 5.0-v spi characteristics diagram number (1) 1. numbers refer to dimensions in figure 20-17 and figure 20-18 . characteristic (2) 2. all timing is shown with respect to 20% v dd and 70% v dd , unless noted; 100 pf load on all spi pins. symbol min max unit operating frequency master slave f op(m) f op(s) f op /128 dc f op /2 f op mhz mhz 1 cycle time master slave t cyc(m) t cyc(s) 2 1 128 ? t cyc t cyc 2 enable lead time t lead(s) 1? t cyc 3 enable lag time t lag(s) 1? t cyc 4 clock (spsck) high time master slave t sckh(m) t sckh(s) t cyc ?25 1/2 t cyc ?25 64 t cyc ? ns ns 5 clock (spsck) low time master slave t sckl(m) t sckl(s) t cyc ?25 1/2 t cyc ?25 64 t cyc ? ns ns 6 data setup time (inputs) master slave t su(m) t su(s) 30 30 ? ? ns ns 7 data hold time (inputs) master slave t h(m) t h(s) 30 30 ? ? ns ns 8 access time, slave (3) cpha = 0 cpha = 1 3. time to data active from high-impedance state t a(cp0) t a(cp1) 0 0 40 40 ns ns 9 disable time, slave (4) 4. hold time to high-impedance state t dis(s) ?40ns 10 data valid time, after enable edge master slave (5) 5. with 100 pf on all spi pins t v(m) t v(s) ? ? 50 50 ns ns 11 data hold time, outputs, after enable edge master slave t ho(m) t ho(s) 0 0 ? ? ns ns
electrical specifications mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 246 freescale semiconductor 20.14 3.0-v spi characteristics diagram number (1) 1. numbers refer to dimensions in figure 20-17 and figure 20-18 . characteristic (2) 2. all timing is shown with respect to 20% v dd and 70% v dd , unless noted; 100 pf load on all spi pins. symbol min max unit operating frequency master slave f op(m) f op(s) f op /128 dc f op /2 f op mhz mhz 1 cycle time master slave t cyc(m) t cyc(s) 2 1 128 ? t cyc t cyc 2 enable lead time t lead(s) 1? t cyc 3 enable lag time t lag(s) 1? t cyc 4 clock (spsck) high time master slave t sckh(m) t sckh(s) t cyc ?35 1/2 t cyc ?35 64 t cyc ? ns ns 5 clock (spsck) low time master slave t sckl(m) t sckl(s) t cyc ?35 1/2 t cyc ?35 64 t cyc ? ns ns 6 data setup time (inputs) master slave t su(m) t su(s) 40 40 ? ? ns ns 7 data hold time (inputs) master slave t h(m) t h(s) 40 40 ? ? ns ns 8 access time, slave (3) cpha = 0 cpha = 1 3. time to data active from high-impedance state t a(cp0) t a(cp1) 0 0 50 50 ns ns 9 disable time, slave (4) 4. hold time to high-impedance state t dis(s) ?50ns 10 data valid time, after enable edge master slave (5) 5. with 100 pf on all spi pins t v(m) t v(s) ? ? 60 60 ns ns 11 data hold time, outputs, after enable edge master slave t ho(m) t ho(s) 0 0 ? ? ns ns
3.0-v spi characteristics mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 247 figure 20-17. spi master timing note note: this first clock edge is generated internally, but is not seen at the spsck pin. ss pin of master held high msb in ss input spsck output spsck output miso input mosi output note 4 5 5 1 4 bits 6?1 lsb in master msb out bits 6?1 master lsb out 11 10 11 7 6 note note: this last clock edge is generated inte rnally, but is not seen at the spsck pin. ss pin of master held high msb in ss input spsck output spsck output miso input mosi output note 4 5 5 1 4 bits 6?1 lsb in master msb out bits 6?1 master lsb out 10 11 10 7 6 a) spi master timing (cpha = 0) b) spi master timing (cpha = 1) cpol = 0 cpol = 1 cpol = 0 cpol = 1
electrical specifications mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 248 freescale semiconductor figure 20-18. spi slave timing note: not defined but normally msb of character just received slave ss input spsck input spsck input miso input mosi output 4 5 5 1 4 msb in bits 6?1 8 6 10 5 11 note slave lsb out 9 3 lsb in 2 7 bits 6?1 msb out note: not defined but normally lsb of character previ ously transmitted slave ss input spsck input spsck input miso output mosi input 4 5 5 1 4 msb in bits 6?1 8 6 10 note slave lsb out 9 3 lsb in 2 7 bits 6?1 msb out 10 a) spi slave timing (cpha = 0) b) spi slave timing (cpha = 1) 11 11 cpol = 0 cpol = 1 cpol = 0 cpol = 1
timer interface module characteristics mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 249 20.15 timer interface module characteristics figure 20-19. input capture timing 20.16 clock generation module characteristics 20.16.1 cgm component specifications characteristic symbol min max unit timer input capture pulse width t th, t tl 2? t cyc timer input capture period t tltl note (1) 1. the minimum period is the number of cycles it take s to execute the interrupt service routine plus 1 t cyc . ? t cyc characteristic symb ol min typ max unit crystal reference frequency f xclk 30 32.768 100 khz crystal load capacitance (1) 1. crystal manufacturer value. c l ? 12.5 ? pf crystal fixed capacitance (2) 2. capacitor on osc1 pin. does not include para sitic capacitance due to package, pin, and board. c 1 ? 15 ?pf crystal tuning capacitance (2) c 2 ? 15 ?pf feedback bias resistor r b 11022m ? series resistor (3) 3. capacitor on osc2 pin. does not include para sitic capacitance due to package, pin, and board. r s 100 330 470 k ? input capture rising edge input capture falling edge input capture both edges t th t tl t tltl t tltl t tltl t tl t th
electrical specifications mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 250 freescale semiconductor 20.16.2 cgm electri cal specifications 20.17 memory characteristics description symbol min typ max unit operating voltage v dd 3.0 ? 5.5 v operating temperature t ?40 25 125 o c crystal reference frequency f rclk 30 32.768 100 khz range nominal multiplier f nom ? 38.4 ? khz vco center-of-range frequency (1) 1. 5.0 v 10% v dd f vrs 38.4 k ? 40.0 m hz medium-voltage vco center-of-range frequency (2) 2. 3.0 v 10% v dd f vrs 38.4 k ? 40.0 m hz vco range linear range multiplier l 1 ? 255 vco power-of-two range multiplier 2 e 1?4 vco multiply factor n 1 ? 4095 vco prescale multiplier 2 p 118 reference divider factor r 1 1 15 vco operating frequency f vclk 38.4 k ? 40.0 m hz bus operating frequency (1) f bus ??8.2mhz bus frequency @ medium voltage (2) f bus ??4.1mhz manual acquisition time t lock ??50ms automatic lock time t lock ??50ms pll jitter (3) 3. deviation of average bus frequency over 2 ms. n = vco multiplier. f j 0? f rclk x 0.025% x 2 p n/4 hz external clock input frequency pll disabled f osc dc ? 32.8 m hz external clock input frequency pll enabled f osc 30 k ? 1.5 m hz characteristic symbol min max unit ram data retention voltage v rdr 1.3 ? v
mc68hc08gp32a mc68hc08gp16a data sheet, rev. 1.0 freescale semiconductor 251 chapter 21 ordering information and mechanical specifications 21.1 introduction this section provides ordering information for the mc68hc08gp32a and mc68hc08gp16a along with the dimensions for: 42-pin shrink dual in-line package (case 858-01) 44-pin plastic quad flat pack (case 824a-01) the following figures show the latest package drawings at the time of th is publication. to make sure that you have the latest package specifications, contact your local freescale sales office. 21.2 mc order numbers these part numbers are generic numbers only. to pl ace an order, rom code must be submitted to the rom processing center (rpc). refer to the customer interface tool (cit) link at: http://freescale.com figure 21-1. device numbering system table 21-1. mc order numbers mc order number operating temperature range (1) 1. temperature designators: c = ?40c to +85c v = ?40c to +105c m = ?40c to +125c package (2) 2. sdip = shrink dual in-line package qfp = quad flat package mc68hc08gp32acb ?40c to +85c 42-pin sdip mc68hc08gp32avb ?40c to +105c mc68hc08gp32amb (3) 3. temperature grade ?m? is availa ble for 5 v operating voltage only. ?40c to +125c mc68hc08gp16acb ?40c to +85c mc68hc08gp16avb ?40c to +105c mc68hc08gp16amb (3) ?40c to +125c mc68hc08gp32acfb ?40c to +85c 44-pin qfp mc68hc08gp32avfb ?40c to +105c mc68hc08gp32amfb (3) ?40c to +125c mc68hc08gp16acfb ?40c to +85c MC68HC08GP16AVFB ?40c to +105c mc68hc08gp16amfb (3) ?40c to +125c m c 6 8 h c 0 8 g p x x a x x x e family package designator temperature range pb free

how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics of their non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp . information in this document is provided solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclai ms any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data shee ts and/or specificati ons can and do vary in different applications and actual perfo rmance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2004, 2006. all rights reserved. mc68hc08gp32a rev. 1.0, 03/2006

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